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 OMAP5912 Applications Processor
Data Manual
Literature Number: SPRS231B December 2003 - Revised March 2004
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to SPRS231A to generate SPRS231B. Scope: SPRS231B is the only revision of this document that has been released.
PAGE(S) NO. 132 133
ADDITIONS/CHANGES/DELETIONS Updated Table 3-56, L3 OCP Initiator Registers Table 3-57, MPU Interface (MPUI) Registers: - updated RESET VALUE column - FFFE:C91C - changed REGISTER NAME and DESCRIPTION - added DSP_MISC_CONFIG (FFFE:C920) - added ENHANCED_CTL (FFFE:C924) Table 3-65, DSP MMU Registers: - changed ACCESS WIDTH of all registers from 32 bits to 16 bits Table 3-71, DSP Timer1 Registers: - updated DSP WORD ADDRESS column Table 3-72, DSP Timer2 Registers: - updated DSP WORD ADDRESS column Table 3-73, DSP Timer3 Registers: - updated DSP WORD ADDRESS column Updated Table 3-74, DSP Watchdog Timer Registers Updated Table 3-78, DSP TIPB Bridge Configuration Registers Updated Table 3-81, DSP Clock Mode Registers Updated Table 3-82, DSP TIPB Bus Switch Registers
136
141
141
142
142 143 144 145
December 2003 - Revised March 2004
SPRS231B
3
Revision History
4
SPRS231B
December 2003 - Revised March 2004
Contents
Contents
Section 1 OMAP5912 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 TMS320C55x DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 ARM926EJ-S RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 16 17 18 18 34 76
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Functional Block Diagram Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 MPU Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 MPU Subsystem Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 DSP Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 DSP I/O Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 DSP External Memory (Managed by MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 MPU and DSP Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 Interrupt Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 CompactFlash Controller (MPU Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.5 LCD Controller (MPU Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.6 LCDCONV (MPU Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.7 Random Number Generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.8 DES/3DES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.9 SHA1/MD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 MPU Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 Display Interface SoSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.3 Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.4 Compact Camera Port (CCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.5 MICROWIRE Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.6 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.7 Pulse-Width Tone (PWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.8 Pulse-Width Light (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.9 Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.10 HDQ/1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.11 Multimedia Card/Secure Digital (MMC/SDIO1) Interface . . . . . . . . . . . . . . . . . . . . . . 3.6.12 MPUIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97 98 101 101 103 137 137 137 138 138 146 148 148 148 148 148 149 149 150 150 150 150 150 151 151 151 152 152 152 152 152 152 153 153
December 2003 - Revised March 2004
SPRS231B
5
Contents
Section 3.6.13 LED Pulse Generators (LPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.14 Frame Adjustment Counter (FAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.15 Operating System (OS) Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.1 Multichannel Buffered Serial Ports (McBSP1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7.2 Multichannel Serial Interfaces (MCSI1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 Mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.2 General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.3 Serial Port Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.4 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . 3.8.5 I2C Master/Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.6 Multichannel Buffered Serial Port (McBSP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.7 Multimedia Card/Secure Digital (MMC/SDIO2) Interface . . . . . . . . . . . . . . . . . . . . . . 3.8.8 General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.9 32-kHz Synchro Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.10 VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller (Memory Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 MPU/DSP Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 MPU Interface (MPUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 MPU/DSP Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Hardware Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 DCT/iDCT Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 Motion Estimation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 Pixel Interpolation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.1 Core and I/O Voltage Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14.2 Core Voltage Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 153 154 154 155 155 156 157 157 157 158 158 160 160 161 162 162 163 164 165 166 167 167 167 168 168 168 168 168 169 169 170
3.7
3.8
3.9 3.10 3.11 3.12
3.13
3.14
4
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
171 171
5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Electrical Characteristics Over Recommended Operating Ambient Temperature Range . . . . 5.4 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 32-kHz Oscillator and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Base Oscillator (12, 13, or 19.2 MHz) and Input Clock . . . . . . . . . . . . . . . . . . . . . . . .
172 172 173 175 176 176 177 177 179
6
SPRS231B
December 2003 - Revised March 2004
Contents
Section 5.7 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 OMAP5912 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 OMAP5912 MPU Core Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 EMIFS/Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 EMIFS/Multiplexed NOR Flash Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 EMIFS/NAND Flash Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.1 McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12.2 McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Interface (SPI) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.1 VLYNQ Slave Mode (External Clock Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15.2 VLYNQ Master Mode (Internal Clock Source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compact Serial Camera Port (CCP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller and LCDCONV Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SoSSI Display Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multimedia Card/Secure Digital (MMC/SD) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal Serial Bus (USB) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Embedded Trace Macrocell (ETM) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 181 181 182 183 183 190 194 198 204 208 212 212 217 221 223 224 224 225 226 227 228 230 232 234 235 236 237 239
5.8
5.9 5.10 5.11 5.12
5.13 5.14 5.15
5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25
6
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
7
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
246 246
December 2003 - Revised March 2004
SPRS231B
7
Figures
List of Figures
Figure 2-1 2-2 OMAP5912 289-Ball ZDY Plastic Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 289-Ball ZZG Plastic Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18 19
3-1 3-2 3-3 3-4 3-5
OMAP5912 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP MMU On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Connections for a Typical System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External RC Circuits for Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97 146 147 169 170
5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator External Crystal With PI-Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Core Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash - Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash - Asynchronous 32-Bit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash - Asynchronous Read - Page Mode 8 x 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash - Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash - Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/MUX NOR Flash - Single Word Asynchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/MUX NOR Flash - Single Word Asynchronous Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/MUX NOR Flash - Synchronous Four-Word Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash - Command Latch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash - Address Latch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash - Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash - Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - Attribute Memory Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - Attribute Memory Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - Common Memory Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - Common Memory Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - I/O Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash - I/O Mode Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR Two SDRAM RD (Read) Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR Two SDRAM WRT (Write) Commands (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM ACTV (Active Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM DCAB (Precharge/Deactivate Row) Command . . . . . . . . . . . . . . . . . . . . . . . .
176 177 178 179 179 181 182 185 186 187 188 189 192 192 193 195 195 196 197 199 199 200 201 202 203 205 205 206 206
8
SPRS231B
December 2003 - Revised March 2004
Figures
Figure 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 5-63 5-64 5-65 EMIFF/SDR SDRAM REFR (Refresh) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM MRS (Mode Register Set) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM - Command and Address Output Timing Definition . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM - Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM - Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . MCSI Master Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI Slave Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface - Transmit and Receive in Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ Transmit and Receive Timings, in Slave or Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK) . . . . . . . . . . . . . . . . . . TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK) . . . . . . . . . . . . . . . . . . SoSSI Display Interface - Read Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SoSSI Display Interface - Write Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Command Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Card Response Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Host Read and Card CRC Status Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ Interface Reading From HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ Interface Writing to HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Communications Between OMAP5912 HDQ and HDQ Slave . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Break (Reset) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-Wire Interface Reading From 1-Wire Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-Wire Interface Writing to 1-Wire Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normal Mode - Half Rate Clock - Rising and Falling Clock Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . Demultiplexed Mode of Full Rate Clock - Rising Clock Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 207 207 210 210 211 215 216 217 218 219 220 222 222 223 225 226 227 229 229 230 231 232 232 233 233 234 235 236 237 237 238 238 238 238 239 240
7-1 7-2
OMAP5912 289-Ball Plastic Ball Grid Array Package (ZDY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 289-Ball MicroStar BGA Plastic Ball Grid Array Package (ZZG) . . . . . . . . . . . . . . . . . .
246 247
December 2003 - Revised March 2004
SPRS231B
9
Tables
List of Tables
Table 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 ZDY Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZZG Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZDY Package Terminal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZZG Package Terminal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCDCONV Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Timer3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Level 1 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB On-the-Go (OTG) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Client Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Real-Time Clock (RTC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPUIO (Keyboard) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Light (PWL) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Tone (PWT) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SDIO1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OS Timer 32-kHz Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Host Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Adjustment Counter (FAC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specially Optimized Screen Interface (SoSSI) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 1 (LPG1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Pulse Generator 2 (LPG2) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 20 27 34 55 76 101 103 104 105 105 105 105 105 106 107 107 108 108 108 109 109 109 109 110 110 110 111 111 111 111 113 114 115 115 116 116 117 117 118
10
SPRS231B
December 2003 - Revised March 2004
Tables
Table 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 I2C1 Registers ......................................................................
Page 118 119 119 120 120 121 122 122 123 123 124 124 125 126 127 128 130 130 131 132 132 132 133 133 133 134 134 135 135 136 136 136 137 137 138 139 141 141 142 142
General-Purpose Timer6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SDIO2 Registers UART3 Registers .............................................................. ...................................................................
MPU GPIO3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU GPIO4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Synchro Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General-Purpose Timer8 Registers .................................................... MPU GPIO1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU GPIO2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU/DSP Shared Mailbox Registers McBSP1 Registers .................................................. ..................................................................
MCSI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP3 Registers .................................................................. ................................................ ........................................... MPU UART TIPB Bus Switch Registers OMAP5912 Configuration Registers
Ultra Low-Power Device Peripheral Registers
...................................................
Device Die Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Production Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L3 OCP Initiator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Interface (MPUI) Registers ...................................................... ......................................... TIPB (Private) Bridge 1 Configuration Registers
Traffic Controller EMIFS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller OCP-T1/OCP-T2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller OCPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traffic Controller EMIFF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU Clock/Reset/Power Mode Control Registers DPLL1 Configuration Register DSP MMU Registers ....................................... ........................................................
................................................................
TIPB (Public) Bridge 2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Timer1 Registers DSP Timer2 Registers DSP Timer3 Registers ............................................................... ............................................................... ...............................................................
DSP Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
December 2003 - Revised March 2004
SPRS231B
11
Tables
Table 3-75 3-76 3-77 3-78 3-79 3-80 3-81 3-82 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 DSP Level 2.0 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Interrupt Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Level 2.1 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP TIPB Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP EMIF Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP I-Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Clock Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Input Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Base Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 Device Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OMAP5912 Device Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPU_RST Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/Flash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NOR Flash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/Mux NOR Flash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/MUX NOR Flash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFS/NAND Flash Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CompactFlash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/SDR SDRAM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFF/DDR SDRAM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP McBSP McBSP McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . . . as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . . . as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . . . as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
Page 142 142 142 143 144 144 144 145 176 178 179 180 181 181 182 182 183 184 190 191 194 194 198 198 204 204 208 209 212 214 217 217 218 218 219 219 220 220 221 221
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . . . McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . . . McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . . MCSI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCSI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
SPRS231B
December 2003 - Revised March 2004
Tables
Table 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 SPI Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ as Slave Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ as Slave Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ as Master Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLYNQ as Master Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Camera Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCP Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD Controller and LCDCONV Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SoSSI Display Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SoSSI Display Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MMC/SD Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Signals (I2C.SDA and I2C.SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB Integrated Transceiver Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MICROWIRE Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDQ/1-Wire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ETM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page 223 223 224 224 225 225 226 227 228 230 230 232 232 234 235 236 236 237 237 239
December 2003 - Revised March 2004
SPRS231B
13
Tables
14
SPRS231B
December 2003 - Revised March 2004
Features
1
OMAP5912 Features
D Low-Power, High-Performance CMOS
Technology - 0.13-m Technology - 1.6-V Core Voltage ARM926EJ-S (MPU) Core - Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets - 16K-Byte Instruction Cache - 8K-Byte Data Cache - Data and Program Memory Management Unit (MMU) - 17-Word Write Buffer - Two 64-Entry Translation Look-Aside Buffers (TLBs) for MMUs TMS320C55x (C55x) DSP Core - One/Two Instructions Executed per Cycle - Dual Multipliers (Two Multiply-Accumulates per Cycle) - Two Arithmetic/Logic Units - Five Internal Data/Operand Buses (3 Read Buses and 2 Write Buses) - 32K x 16-Bit On-Chip Dual-Access RAM (DARAM) (64K Bytes) - 48K x 16-Bit On-Chip Single-Access RAM (SARAM) (96K Bytes) - Instruction Cache (24K Bytes) - Video Hardware Accelerators for DCT, iDCT, Pixel Interpolation, and Motion Estimation for Video Compression 250K Bytes of Shared Internal SRAM Memory Traffic Controller (TC) - 16-Bit EMIFS to Access up to 256M Bytes of Flash (for Burst, Programmable NOR Flash) - 16-Bit EMIFF to Access up to 128M Bytes of SDRAM, Mobile SDRAM, or Mobile DDR DSP Memory Management Unit Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control DSP Peripherals - Three 32-Bit Timers and Watchdog Timer - Six-Channel DMA Controller - Two Multichannel Buffered Serial Ports - Two Multichannel Serial Interfaces - Three 32-Bit Timers and Watchdog Timer - USB 1.1 Host and Client Controllers - USB On-the-Go (OTG) Controller - 3 USB Ports, One With an Integrated Transceiver - Specially Optimized Screen Interface (SoSSI) - Compact Camera Port Interface For Parallel CMOS Sensors - Real-Time Clock (RTC) - Pulse-Width Tone (PWT) Interface - Pulse-Width Light (PWL) Interface - Keyboard Matrix Interface (6 x 5 or 8 x 8) - HDQ/1-Wire Interface - Multimedia Card (MMC) and Secure Digital (SD) Interface - CompactFlash Controller - Up to 16 MPU General-Purpose I/Os - Two LED Pulse Generators (LPGs) - ETM9 Trace Module for ARM926EJ-S Debug - 16-/18-Bit LCD Controller With Dedicated System DMA Channel - 32-kHz Operating System (OS) Timer Shared Peripherals - 8 General-Purpose Timers - Serial Port Interface (SPI) - VLYNQ Interface (WLAN 802.11x) - Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting SIR mode for IrDA) - Inter-Integrated Circuit (I2C) Master and Slave Interface - Multimedia Card (MMC) and Secure Digital (SD) Interface - Multichannel Buffered Serial Port (McBSP) - Up to 64 Shared General-Purpose I/Os - 32-kHz Synchro Counter Hardware Accelerators for Cryptographic Functions - Random Number Generation - DES and 3DES - SHA-1 and MD5 Individual Power-Saving Modes for MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE Std 1149.1 (JTAG) Boundary Scan Logic Two 289-Ball Lead-Free BGA (Ball Grid Array) Packages (ZDY and ZZG)
D
D
D
D D
D
D D D
D D D D
D MPU Peripherals
All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
December 2003 - Revised March 2004
SPRS231B
15
PRODUCT PREVIEW
Introduction
2
Introduction
This section describes the main features of the OMAP5912 device, lists the terminal assignments, and describes the function of each terminal. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
2.1
Description
OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM core. The OMAP5912 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS software kernel foundation, and is available in two 289-ball lead-free ball grid array (BGA) packages (ZDY and ZZG). The OMAP5912 device is targeted at the following applications: * * Applications Processing Devices Mobile Communications - - - - * * * * * * WAN 802.11X Bluetooth GSM, GPRS, EDGE CDMA
PRODUCT PREVIEW
Video and Image Processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced Speech Applications (text-to-speech, speech recognition) Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and Other GSM Speech Codecs) Graphics and Video Acceleration Generalized Web Access Data Processing
TMS320C55x, C55x, VLYNQ, OMAP, and DSP/BIOS are trademarks of Texas Instruments. ARM926EJ-S and ETM9 are trademarks of ARM Limited in the EU and other countries. Thumb and ARM are registered trademarks of ARM Limited in the EU and other countries. 1-Wire is a registered trademark of Dallas Semiconductor Corporation. CompactFlash is a trademark of CompactFlash Association. Bluetooth is a trademark owned by Bluetooth SIG, Inc. Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.
16
SPRS231B
December 2003 - Revised March 2004
Introduction
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5912 device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU. The C55x DSPs support a variable byte width instruction set for improved code density. The instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The OMAP5912 DSP core also includes a 24K-byte instruction cache to minimize external memory accesses, improving data throughput and conserving system power.
2.1.1.1
DSP Tools Support
The 55x DSP core is supported by the industry's leading eXpressDSP software environment including the Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS software kernel foundation, the TMS320 DSP Algorithm Standard, and the industry's largest third-party network. Code Composer Studio features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable real-time software foundation available for no cost to users of Texas Instruments' DSP products, providing a preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead. The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of algorithms from different teams, sites, or third parties into the application framework. Texas Instruments' extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions to customers.
2.1.1.2
DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP Library (DSPLIB) features over 50 C-callable software routines (FIR/IIR filters, Fast Fourier Transforms (FFTs), and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over 20 software routines highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP code generation tools. These imaging functions support a wide range of applications that include compression, video processing, machine vision, and medical imaging.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments. 17
December 2003 - Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
2.1.2 ARM926EJ-S RISC Processor
The MPU core is a ARM926EJ-S reduced instruction set computer (RISC) processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The MPU core incorporates: * * * A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).
The OMAP5912 device uses the ARM926EJ-S core in little-endian mode only. To minimize external memory access time, the ARM926EJ-S includes an instruction cache, data cache, and a write buffer. In general, these are transparent to program execution.
2.2
Terminal Assignments
Figure 2-1 illustrates the ball locations for the 289-ball ZDY package and Figure 2-2 illustrates the ball locations for the 289-ball ZZG package. Figure 2-1 and Figure 2-2 are used in conjunction with Table 2-1 and Table 2-2, respectively, to locate signal names and ball grid numbers. BGA ball numbers in Table 2-1 and Table 2-2 are read from left-to-right, top-to-bottom.
PRODUCT PREVIEW
U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Bottom View
Figure 2-1. OMAP5912 289-Ball ZDY Plastic Ball Grid Array (Bottom View)
18
SPRS231B
December 2003 - Revised March 2004
Introduction
Y V T P M K H F D B
AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 Bottom View
Figure 2-2. OMAP5912 289-Ball ZZG Plastic Ball Grid Array (Bottom View) In Table 2-1 and Table 2-2, signals with multiplexed functions are highlighted in gray. Signals within a multiplexed pin name are separated with forward slashes as follows: * signal1/signal2/signal3 (e.g., MPUIO1/RTCK/SPIF.SCK)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed by a period, and then the signal name; as follows: * peripheral1.signal1 (i.e., MCSI1.DOUT)
December 2003 - Revised March 2004
SPRS231B
19
PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments
ZDY BALL NO. A1 A5 A9 SIGNAL SDRAM.A[1] SDRAM.D[3] CVDDDLL LCD.P[12](0)/ Z_STATE(1)/ SOSSI.D[12](6)/ GPIO33(7) LCD.P[0](0)/ Z_STATE(1)/ SOSSI.D[0](6) SDRAM.D[0] SDRAM.D[10] ZDY BALL NO. A2 A6 A10 SIGNAL SDRAM.DQSL SDRAM.CLKX SDRAM.A[7] LCD.PCLK(0)/ Z_STATE(1)/ SOSSI.WR(6) ZDY BALL NO. A3 A7 A11 SIGNAL SDRAM.D[6] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ SOSSI.D[10](6)/ GPIO31(7) SDRAM.A[0] SDRAM.D[5] SDRAM.D[15] LCD.P[11](0)/ Z_STATE(1)/ SOSSI.D[11](6)/ GPIO32(7) ZDY BALL NO. A4 A8 A12 SIGNAL SDRAM.D[2] SDRAM.DQMU SDRAM.DQSH LCD.P[6](0)/ Z_STATE(1)/ SOSSI.D[6](6)
A13
A14
A15
A16
A17 B4 B8
B1 B5 B9
DVDD5 SDRAM.D[1] SDRAM.D[12]
B2 B6 B10
B3 B7 B11
SDRAM.D[4] SDRAM.D[7] SDRAM.D[13] LCD.VS(0)/ Z_STATE(1)/ SOSSI.RD(6)
PRODUCT PREVIEW
B12
SDRAM.D[9]
B13
SDRAM.CKE
B14
B15
B16 C3 C7
LCD.P[1](0)/ Z_STATE(1)/ SOSSI.D[1](6) SDRAM.A[3] SDRAM.DQML
B17 C4 C8
KB.C[2](0)/ GPIO61(7) SDRAM.BA[1] SDRAM.A[5] LCD.P[15](0)/ Z_STATE(1)/ SOSSI.D[15](6)/ GPIO2(7) LCD.P[2](0)/ Z_STATE(1)/ SOSSI.D[2](6) FLASH.A[1](0) DVDD4
C1 C5 C9
FLASH.A[6](0) SDRAM.BA[0] SDRAM.D[8] LCD.P[8](0)/ Z_STATE(1)/ SOSSI.D[8](6)/ GPIO29(7) KB.C[1](0)/ MPUIO6(1) SDRAM.RAS DVDD4 LCD.P[14](0)/ Z_STATE(1)/ SOSSI.D[14](6)/ GPIO35(7) KB.C[4](0)/ GPIO27(7) FLASH.A[4](0) SDRAM.CS
C2 C6 C10
FLASH.A[2](0) SDRAM.A[8] SDRAM.D[14]
C11
CVDD
C12
C13
C14
DVDD1
C15 D2 D6
LCD.P[5](0)/ Z_STATE(1)/ SOSSI.D[5](6) FLASH.A[5](0) DVDD4
C16 D3 D7
C17 D4 D8
D1 D5 D9
FLASH.A[8](0) SDRAM.CAS SDRAM.A[4] LCD.P[7](0)/ Z_STATE(1)/ SOSSI.D[7](6) KB.R[3](0)/ MPUIO13(1)/ VLYNQ.TX0(2) FLASH.A[3](0) SDRAM.A[12]
D10
SDRAM.A[13]
D11
DVDD4
D12
D13
D14 E1 E5
LCD.P[3](0)/ Z_STATE(1)/ SOSSI.D[3](6) FLASH.A[9](0) VSS
D15 E2 E6
LCD.HS(0)/ Z_STATE(1)/ SOSSI.CS(6) FLASH.A[7](0) SDRAM.WE
D16 E3 E7
D17 E4 E8
Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
20
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL LCD.P[13](0)/ Z_STATE(1)/ SOSSI.D[13](6)/ GPIO34(7) KB.C[3](0)/ GPIO63(6) ZDY BALL NO. SIGNAL
E9
SDRAM.A[11]
E10
SDRAM.A[6]
E11
E12
LCD.P[4](0)/ Z_STATE(1)/ SOSSI.D[4](6) KB.R[2[(0)/ MPUIO10(1)/ VLYNQ.CLK(2) FLASH.A[25] SDRAM.A[2] LCD.P[9](0)/ Z_STATE(1)/ SOSSI.D[9](6)/ GPIO30(7) KB.R[0](0)/ MPUIO8(1)/ VLYNQ.RX1(2) FLASH.A[15](0) FLASH.A[17] CVDD3 MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
E13
VSS KB.R[1](0)/ MPUIO9(1)/ VLYNQ.RX0(2) FLASH.A[20]
E14
NC
E15
E16
E17 F4
F1 F5
FLASH.A[11](0) FLASH.A[12](0)
F2 F6
FLASH.A[10](0) VSS LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2)/ SOSSI.CMD(6) KB.C[0](0)/ MPUIO0(1) DVDD5 FLASH.A[16](0) CVDD2 MCBSP1.CLKS(0)/ SOSSI.TE(6)/ GPIO62(7)
F3 F7
F8
SDRAM.A[10]
F9
SDRAM.A[9]
F10
F11
F12
VSS MCBSP1.CLKX(0)/ GPIO54(7) FLASH.A[13](0) VSS
F13
KB.R[4](0)/ MPUIO15(1)/ VLYNQ.TX1(2) KB.C[5](0)/ GPIO28(7) FLASH.A[14](0) CVDD2
F14
F15
F16 G3 G7
F17 G4 G8
G1 G5 G9
G2 G6 G10
G11
VSS
G12
DVDD1
G13
G14
G15
MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7) FLASH.A[22] FLASH.ADV
G16
CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7) FLASH.A[18] CVDD2
G17
MCBSP1.DR(0)/ GPIO51(7) FLASH.A[19] VSS CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ LOW_STATE (6)/ GPIO57(7)
H1
LDO.FILTER
H2 H6
H3 H7
H4 H8
H5 H9
FLASH.A[21] VSS CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7)
H10
VSS
H11
CVDD3
H12
H13

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
21
PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD/ SPI.DO(3)/ GPIO34(7) FLASH.A[23] ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL
H14
MPU_BOOT(0)/ USB1.SUSP(2)
H15
H16
CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7) FLASH.CS1(0)/ FLASH.CS1L(1)
H17
CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7)
J1
FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7) GPIO62(0)/ FLASH.CS0(1)
J2
J3
J4
FLASH.A[24] FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2) CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ SPI.DI(3)/ GPIO38(7) CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7)
J5
J6
FLASH.CS3(0)/ GPIO3(7)
J7
FLASH.D[3]
J8
PRODUCT PREVIEW
J9
VSS
J10
CVDD3
J11
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7)
J12
J13
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3) CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) NC VSS CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ LOW_STATE(6)/ GPIO37(7) GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)/ VLYNQ.TX1(4)
J14
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7)
J15
DVDD8
J16
J17
K1
FLASH.CLK(0)/ FLASH.CS2UOE(1)
K2
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) FLASH.D[6] VSS GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3)/ VLYNQ.TX0(4)
K3
FLASH.CS2U(0)/ GPIO5(1)
K4 K8
K5 K9
CVDD VSS GPIO11(0)/ HDQ(1)/ VLYNQ.RX1(4)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) LOW_STATE(0)/ UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[5]
K6 K10
K7 K11
FLASH.D[12] CVDD3 UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7)
K12
K13
K14
K15
K16
K17
L1
FLASH.D[0]
L2
FLASH.D[2]
L3

DVDD5
L4
L5
FLASH.D[8]
L6
FLASH.RDY(0)/ GPIO10(1)
Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
22
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7) MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6) ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7) GPIO6(0)/ SPI.CS1(1)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
L7
VSS
L8
L9
CVDDRTC
L10
L11
VSS
L12
L13
GPIO3(0)/ SPI.CS3(1)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7) GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3)/ VLYNQ.CLK(4) FLASH.D[10] MMC.CLK(0)/ SSI.CARDY(6)/ GPIO57(7) VSS
L14
L15
M2 M6
FLASH.D[4] VSS
M3 M7
FLASH.D[11] CVDD I2C.SDA(0)/ GPIO48(7)
M4 M8
M5 M9
FLASH.OE UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7) DVDD9 GPIO4(0)/ SPI.CS2(1)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4) FLASH.D[15]
M10
TMS MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[7]
M11
M12
M13
M14
M15
GPIO1(0)/ UART3.RTS(1)
M16
GPIO2(0)/ SPI.CLK(1)/ ETM.PSTAT[4](5)/ RTDX.D[0] (7) FLASH.RP(0)/ FLASH.CS2UWE(1) MMC.CMD/SPI.DO(0)/ CFLASH.CD2(3)/ SSI.CADATA(6)/ GPIO55(7)
M17
N1
N2
FLASH.D[9] MCBSP2.FSX(0)/ VLYNQ.RX1(3)/ GPIO21(7) MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
N3
N4
N5
VSS
N6
N7
N8
PWRON_RESET
N9
RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ CCP.CLKM(6)/ GPIO55(7)
N10
N11
EMU1
N12
RST_OUT(0)/ GPIO41(7)
N13
VSS
N14
MPU_RST(0)/ MPUIO14(6)
N15
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
N16
MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4)

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
23
PRODUCT PREVIEW
GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7)
L16
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3)/ VLYNQ.RX0[4]
L17
M1
FLASH.D[1]
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL GPIO0(0)/ SPI.RDY(1)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7) MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ SSI.ACWAKE(6)/ GPIO56(7) I2C.SCL ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL
N17
P1
FLASH.D[13]
P2
OSC1_OUT
P3
FLASH.WE
P4
P5
UART2.BCLK(0)/ SYS_CLK_IN(6)
P6
UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
P7
GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD/SPI.DO(6) MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ CCP.DATAP(6)/ GPIO18(7)/ MCBSP3.DOUT_HIZ UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4) OSC1_IN
P8
P9
PRODUCT PREVIEW
MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)/ CFLASH.CD1(3)/ SSI.ACFLAG(6)
P10
RTC_ON_NOFF(0)/ CCP.CLKP(6)
P11
P12
P13
TCK
P14
UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7) FLASH.D[14]
P15
P16
P17
CVDDA LOW_STATE(0)/ UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT0/SPI.DI(0)/ Z_STATE(1)/ CFLASH.IOIS16(3)/ SSI.ACRDY(6)/ GPIO58(7) BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7)
R1
R2
R3
FLASH.WP
R4
R5
MCBSP2.FSR(0)/ GPIO12(1)/ VLYNQ.RX0(3)
R6
MPUIO3(0)/ MMC2.DAT1(6)
R7
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7) LOW_STATE(0)/ UART1.RTS(1)/ UART1.IRSHDN(2)/ VLYNQ.TX0(3)/ Z_STATE(6)/ GPIO39(7)
R8
R9
VSS
R10
DVDDRTC
R11
R12
R13
TRST
R14
CONF

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
24
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7) ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL
R15
R16
Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
R17
Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7)
T1
FLASH.CS1U(0)/ GPIO16(7)
T2
USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7)
T3
CVDD1
T4
LOW_STATE(0)/ UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/ LOW_STATE(6) MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) LOW_STATE(0)/ UART1.TX(1)/ UART1.IRTX(2)/ CCP.DATAM (6)
T5
MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
T6
DVDD3
T7
MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7)
T8
T9
MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)/ CFLASH.RESET(3)/ SSI.CAFLAG(6)
T10
DVDD6
T11
CLK32K_IN
T12
T13
DVDD7
T14
RTCK
T15
TDO/ VLYNQ.TX0
T16
CVDD
T17
BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6) UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7)
U1
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
U2
DVDD2
U3
MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7)
U4
U5
MCBSP2.CLKX(0)/ VLYNQ.TX1(3)/ GPIO20(7)
U6
MCBSP2.CLKR(0)/ GPIO11(1)/ VLYNQ.CLK(3)
U7
GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0/SPI.DI(6)
U8
U9
MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2)/ CFLASH.IREQ(3)/ SSI.ACDATA(6)
U10
OSC32K_OUT
U11
OSC32K_IN
U12

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
25
PRODUCT PREVIEW
Introduction
Table 2-1. ZDY Package Terminal Assignments (Continued)
ZDY BALL NO. SIGNAL ZDY BALL NO. SIGNAL Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7) ZDY BALL NO. SIGNAL MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7) ZDY BALL NO. SIGNAL
U13
UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
U14
U15
U16
EMU0
U17

TDI
Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
PRODUCT PREVIEW
26 SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-2. ZZG Package Terminal Assignments
ZZG BALL NO. A1 A7 SIGNAL SDRAM.A[3] DVDD4 ZZG BALL NO. A2 A9 SIGNAL SDRAM.A[0] CVDD2 LCD.P[13](0)/ Z_STATE(1)/ SOSSI.D[13](6)/ GPIO34(7) VSS VSS SDRAM.A[5] ZZG BALL NO. A3 A11 SIGNAL CVDD2 CVDDDLL ZZG BALL NO. A5 A13 SIGNAL DVDD4 VSS LCD.P[5](0)/ Z_STATE(1)/ SOSSI.D[5](6) SDRAM.BA[0] VSS SDRAM.A[9]
A15
CVDD
A17
A19
DVDD1
A20
A21 B4 B8
VSS SDRAM.CAS SDRAM.A[10]
B1 B5 B9
B2 B6 B10
SDRAM.A[1] SDRAM.A[2] DVDD4 LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2)/ SOSSI.CMD(6) LCD.P[6](0)/ Z_STATE(1)/ SOSSI.D[6](6)
B3 B7 B12
B13
CVDD3
B14
DVDD4
B15
B16
VSS
B17
B18
LCD.VS(0)/ Z_STATE(1)/ SOSSI.RD(6)
B19
B20
CVDD3
B21 C4 C8 C12
LCD.P[1](0)/ Z_STATE(1)/ SOSSI.D[1](6) SDRAM.D[6] SDRAM.DQML SDRAM.D[15] LCD.P[14](0)/ Z_STATE(1)/ SOSSI.D[14](6)/ GPIO35(7) LCD.HS(0)/ Z_STATE(1)/ SOSSI.CS(6) SDRAM.DQSL SDRAM.D[7]
C1 C5 C9 C13
FLASH.A[3](0) SDRAM.D[2] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ SOSSI.D[10](6)/ GPIO31(7) KB.C[4](0)/ GPIO27(7) SDRAM.D[4] SDRAM.CLKX
C2 C6 C10 C14
DVDD5 SDRAM.D[1] SDRAM.D[8] SDRAM.DQSH
C3 C7 C11 C15
SDRAM.BA[1] SDRAM.D[5] SDRAM.D[12] LCD.PCLK(0)/ Z_STATE(1)/ SOSSI.WR(6) LCD.P[2](0)/ Z_STATE(1)/ SOSSI.D[2](6)
C16
C17
C18
LCD.P[7](0)/ Z_STATE(1)/ SOSSI.D[7](6)
C19
C20 D4 D8
C21 D5 D9
D2 D6 D10
FLASH.A[5](0) SDRAM.D[0] SDRAM.DQMU
D3 D7 D11
FLASH.A[2](0) SDRAM.D[3] SDRAM.D[10] LCD.P[15](0)/ Z_STATE(1)/ SOSSI.D[15](6)/ GPIO2(7)
D12
SDRAM.D[14]
D13
SDRAM.D[13]
D14
SDRAM.D[9]
D15

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
27
PRODUCT PREVIEW
LCD.P[11](0)/ Z_STATE(1)/ SOSSI.D[11](6)/ GPIO32(7)
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL LCD.P[9](0)/ Z_STATE(1)/ SOSSI.D[9](6)/ GPIO30(7) KB.C[1](0)/ MPUIO6(1) FLASH.A[4](0) KB.R[3](0)/ MPUIO13(1)/ VLYNQ.TX0(2) ZZG BALL NO. SIGNAL LCD.P[8](0)/ Z_STATE(1)/ SOSSI.D[8](6)/ GPIO29(7) FLASH.A[25] ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL
D16
D17
D18
LCD.P[0](0)/ Z_STATE(1)/ SOSSI.D[0](6) CVDD2 KB.C[3](0)/ GPIO63(6)
D19
KB.C[2](0)/ GPIO61(7)
D20
E1
E2
E3
FLASH.A[7](0) KB.R[4](0)/ MPUIO15(1)/ VLYNQ.TX1(2) FLASH.A[9](0)
E4
E5
NC
E18
E19
E20
E21
DVDD1
F2
FLASH.A[20] KB.R[1](0)/ MPUIO9(1)/ VLYNQ.RX0(2) FLASH.A[11](0) SDRAM.A[4] LCD.P[3](0)/ Z_STATE(1)/ SOSSI.D[3](6) MCBSP1.CLKX(0)/ GPIO54(7) SDRAM.RAS SDRAM.A[13] MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7)
F3
F4
FLASH.A[6](0) VSS SDRAM.CS
F18 G2 G9
KB.C[0](0)/ MPUIO0(1) FLASH.A[12](0) SDRAM.A[8] LCD.P[12](0)/ Z_STATE(1)/ SOSSI.D[12](6)/ GPIO33(7) MCBSP1.CLKS(0)/ SOSSI.TE(6)/ GPIO62(7) FLASH.A[14](0) SDRAM.A[11] KB.R[2[(0)/ MPUIO10(1)/ VLYNQ.CLK(2)
F19 G3 G10
F20 G4 G11
VSS FLASH.A[10](0) SDRAM.A[7] KB.R[0](0)/ MPUIO8(1)/ VLYNQ.RX1(2)
PRODUCT PREVIEW
G1 G8
G12
SDRAM.A[6]
G13
G14
G18
G19 H3 H9
KB.C[5](0)/ GPIO28(7) FLASH.A[15](0) SDRAM.A[12] LCD.P[4](0)/ Z_STATE(1)/ SOSSI.D[4](6) CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ LOW_STATE(6)/ GPIO57(7) FLASH.A[19] CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7)
G20 H4 H10
G21 H7 H11
H2 H8 H12
DVDD5 SDRAM.WE SDRAM.CKE MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
H13
H14
H15
H18
H19
H20
MCBSP1.DR(0)/ GPIO51(7)
J1
LDO.FILTER
J2
FLASH.A[17]
J3
J4
FLASH.A[18] CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7)
J7
FLASH.A[8](0) CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7)
J8
FLASH.A[1](0) CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD SPI.DO(3)/ GPIO34(7)
J14
J15
J18
J19

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
28
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. J20 SIGNAL MPU_BOOT(0)/ USB1.SUSP(2) ZZG BALL NO. J21 SIGNAL ZZG BALL NO. K2 SIGNAL ZZG BALL NO. K3 SIGNAL
CVDD3
VSS
FLASH.A[23] CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7)
K4
FLASH.A[22]
K7
FLASH.A[16](0)
K8
FLASH.A[13](0)
K14
K15
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7) NC
K18
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7) FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7) UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7)
K19
CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7) FLASH.ADV CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ SPI.DI(3)/ GPIO38(7)
K20
VSS
L1
L3
L4
L7
FLASH.A[24]
L8
FLASH.A[21]
L14
L15
L18
L19
CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2) GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7) VSS
L21
DVDD8
M2
CVDD
M3
FLASH.CS1(0)/ FLASH.CS1L(1) GPIO2(0)/ SPI.CLK(1)/ ETM.PSTAT[4](5)/ RTDX.D[0] (7) GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)/ VLYNQ.TX1(4)
M4
M7
GPIO62(0)/ FLASH.CS0(1) LOW_STATE(0)/ UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[1]
M8
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ LOW_STATE(6)/ GPIO37(7) FLASH.CLK(0)/ FLASH.CS2UOE(1) Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7)
M14
M15
M18
M19
M20
N1
N2
N3
N4
FLASH.D[0]
N7
FLASH.D[2]
N8
FLASH.CS3(0)/ GPIO3(7)
N14
N15
MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6)

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
29
PRODUCT PREVIEW
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3)
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3)/ VLYNQ.CLK(4) FLASH.CS2U(0)/ GPIO5(1) USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7) ZZG BALL NO. SIGNAL GPIO11(0)/ HDQ(1)/ VLYNQ.RX1(4)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) FLASH.D[4] MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7) MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7) GPIO4(0)/ SPI.CS2(1)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4) ZZG BALL NO. SIGNAL GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3)/ VLYNQ.TX0(4) FLASH.D[5] MMC.CMD/SPI.DO(0)/ CFLASH.CD2(3)/ SSI.CADATA(6)/ GPIO55(7) Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
N18
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3)/ VLYNQ.RX0[4] FLASH.D[3]
N19
N20
N21
P2
P3
P4
P7
P8
FLASH.D[11]
P9
P10
P11
PRODUCT PREVIEW
P12
VSS
P13
CLK32K_IN
P14
P15
P18
GPIO3(0)/ SPI.CS3(1)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7)
P19
GPIO6(0)/ SPI.CS1(1)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
P20
R1
DVDD5
R2
FLASH.D[6]
R3
FLASH.D[7]
R4
FLASH.D[8]
R8
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
R9
UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7) CVDD3
R10
MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7) UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7) VSS
R11
MMC.DAT0/SPI.DI(0)/ Z_STATE(1)/ CFLASH.IOIS16(3)/ SSI.ACRDY(6)/ GPIO58(7) GPIO0(0)/ SPI.RDY(1)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) FLASH.D[9]
R12
PWRON_RESET
R13
R14
R18
R19
GPIO1(0)/ UART3.RTS(1)
R20

R21
T2
T3
FLASH.D[10]
Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
30
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[13] ZZG BALL NO. SIGNAL
T4
FLASH.D[14]
T18
I2C.SCL
T19
T20
MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4) FLASH.OE
U1
FLASH.D[12] UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7) FLASH.RDY(0)/ GPIO10(1) LOW_STATE(0)/ UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2)/ CFLASH.IREQ(3)/ SSI.ACDATA(6)
U2
VSS
U3
U4
U18
U19
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
U20
MPU_RST(0)/ MPUIO14(6)
U21
DVDD9
V6
V7
MCBSP2.CLKR(0)/ GPIO11(1)/ VLYNQ.CLK(3)
V8
MPUIO3(0)/ MMC2.DAT1(6)
V9
MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6)
V10
V11
MMC.CLK(0)/ SSI.CARDY(6)/ GPIO57(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ SSI.ACWAKE(6)/ GPIO56(7) UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4)
V12
DVDDRTC
V13
OSC32K_IN
V14
UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
V15
V16
EMU0
V17
TMS
V18
CONF
V19
V20
I2C.SDA(0)/ GPIO48(7)
W1
FLASH.RP(0)/ FLASH.CS2UWE(1) LOW_STATE(0)/ UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/ LOW_STATE(6)
W2
FLASH.WE
W3
OSC1_OUT
W4
USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7)
W5

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
31
PRODUCT PREVIEW
V2
V3
FLASH.D[15]
V4
FLASH.WP
V5
MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7)
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ CCP.CLKM(6)/ GPIO55(7)
W6
MCBSP2.FSR(0)/ GPIO12(1)/ VLYNQ.RX0(3) MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)/ CFLASH.RESET(3)/ SSI.CAFLAG(6) MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ CCP.DATAP(6)/ GPIO18(7)/ MCBSP3.DOUT_HIZ
W7
MCBSP2.FSX(0)/ VLYNQ.RX1(3)/ GPIO21(7) MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)/ CFLASH.CD1(3)/ SSI.ACFLAG(6)
W8
GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0/SPI.DI(6)
W9
W10
W11
W12
CVDDRTC
W13
W14
W15
PRODUCT PREVIEW
BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7)
W16
Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7)
W17
EMU1
W18
TCK
W19
BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6)
W20
VSS
W21
UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7) UART2.BCLK(0)/ SYS_CLK_IN(6) GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD/SPI.DO(6)
Y1
FLASH.CS1U(0)/ GPIO16(7) UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
Y2
OSC1_IN MCBSP2.CLKX(0)/ VLYNQ.TX1(3)/ GPIO20(7) MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7) TDI
Y3
VSS
Y4
Y5
Y6
Y7
DVDD3
Y8
Y9
CVDD
Y10
Y12
RTC_ON_NOFF(0)/ CCP.CLKP(6)
Y13
VSS
Y14
LOW_STATE(0)/ UART1.TX(1)/ UART1.IRTX(2)/ CCP.DATAM (6) TRST
Y15
Y16
DVDD7
Y17
RTCK
Y18
Y19
Y20
CVDD
Y21
CVDDA
Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
32
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-2. ZZG Package Terminal Assignments (Continued)
ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL ZZG BALL NO. SIGNAL MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
AA1
VSS
AA2
DVDD2
AA3
CVDD1
AA5
AA7
VSS
AA9
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7) MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
AA11
DVDD6
AA13
OSC32K_OUT
AA15
LOW_STATE(0)/ UART1.RTS(1)/ UART1.IRSHDN(2)/ VLYNQ.TX0(3)/ Z_STATE(6)/ GPIO39(7) VSS
AA17
AA19
TDO/ VLYNQ.TX0
AA20
RST_OUT(0)/ GPIO41(7)

Z_STATE = high-impedance "NC" denotes "No Connect". LOW_STATE = 0 NOTES: 1. Shading denotes signals with multiplexed functions. 2. The number within parenthesis at the end of a signal name denotes the Pin Mux setting (see the MUX CTRL SETTING column in Table 2-3 and Table 2-4).
December 2003 - Revised March 2004
SPRS231B
33
PRODUCT PREVIEW
AA21
Introduction
2.3
Terminal Characteristics and Multiplexing
Table 2-3 describes terminal characteristics and the signals multiplexed on each ball for the ZDY package. Table 2-4 describes terminal characteristics and the signals multiplexed on each ball for the ZZG package. The table column headers are explained below: * * * * * * * * BALL NO.: The package ball number. SIGNAL NAME: The names of all the signals that are multiplexed on each ball. TYPE: The signal direction. MUX CTRL SETTING: Shows control of multiplexing modes. PULLUP/PULLDN: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled or disabled via software. BUFFER STRENGTH: Drive strength of the associated output buffer. OTHER: Contains various terminal information, such as buffer type, boundary scan capability, and gating/inhibit functionality. RESET STATE: The state of the terminal at reset. SUPPLY: The voltage supply which powers the terminal's I/O buffers. NOTE: Care must be taken to avoid assigning multiple balls to the same signal. Violations may cause unexpected results. Table 2-3. ZDY Package Terminal Characteristics
PRODUCT PREVIEW
*
ZDY BALL NO. E7 A12 A2 D5 D4 C7 A8

SIGNAL NAME SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU
TYPE O I/O I/O O O O O
MUX CTRL SETTING NA NA NA NA NA NA NA
PULLUP/ PULLDN
BUFFER STRENGTH 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv)
OTHER A A, K A, K A A A, K A, K
RESET STATE# 1 0 0 1 1 0 0
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
34
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. E6 D10 E8 E9 F8 F9 C6 A10 E10 B9 C8 C3 F7 A1 B2 C4 C5 B10 C10 B11 B9 A11 B8 B12 C9 B7 A3 B6 B3 A5 A4 B5 B4 A7 A6 B13 F10 SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE SOSSI.CMD A14 LCD.PCLK Z_STATE SOSSI.WR

SIGNAL NAME SDRAM.WE SDRAM.A[13:0]
TYPE O O
MUX CTRL SETTING NA NA
PULLUP/ PULLDN
BUFFER STRENGTH 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
OTHER A A
RESET STATE# 1 0
SUPPLY DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
O I/O
NA NA
3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv)
A A, K
0 0
DVDD4 DVDD4
O O O O O Z O O Z O
NA NA NA RegD[11:9] = 000 RegD[11:9] = 001 RegD[11:9] = 010 RegD[11:9] = 110 RegD[17:15] = 000 RegD[17:15] = 001 RegD[17:15] = 110
3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 2 mA (Lv) 6 mA (Hv)
A, K A, K A A, F, G1
U 0 1 0
DVDD4 DVDD4 DVDD4 DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
35
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. C12 SIGNAL NAME LCD.P[15] Z_STATE SOSSI.D[15] GPIO2 D12 LCD.P[14] Z_STATE SOSSI.D[14] GPIO35 E11 LCD.P[13] Z_STATE SOSSI.D[13] GPIO34 A13 LCD.P[12] Z_STATE SOSSI.D[12] GPIO33 B14 LCD.P[11] Z_STATE SOSSI.D[11] GPIO32 A15 LCD.P[10] Z_STATE SOSSI.D[10] GPIO31 F11 LCD.P[9] Z_STATE SOSSI.D[9] GPIO30 B15 LCD.VS Z_STATE SOSSI.RD
TYPE O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z O
MUX CTRL SETTING RegD[20:18] = 000 RegD[20:18] = 001 RegD[20:18] = 110 RegD[20:18] = 111 RegD[23:21] = 000 RegD[23:21] = 001 RegD[23:21] = 110 RegD[23:21] = 111 RegD[26:24] = 000 RegD[26:24] = 001 RegD[26:24] = 110 RegD[26:24] = 111 RegD[29:27] = 000 RegD[29:27] = 001 RegD[29:27] = 110 RegD[29:27] = 111 RegE[2:0] = 000 RegE[2:0] = 001 RegE[2:0] = 110 RegE[2:0] = 111 RegE[5:3] = 000 RegE[5:3] = 001 RegE[5:3] = 110 RegE[5:3] = 111 RegE[8:6] = 000 RegE[8:6] = 001 RegE[8:6] = 110 RegE[8:6] = 111 RegE[11:9] = 000 RegE[11:9] = 001 RegE[11:9] = 110
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
F, A, G1
0
DVDD1
PRODUCT PREVIEW
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
36
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. C13 SIGNAL NAME LCD.P[8] Z_STATE SOSSI.D[8] GPIO29 D13 LCD.P[7] Z_STATE SOSSI.D[7] A16 LCD.P[6] Z_STATE SOSSI.D[6] C15 LCD.P[5] Z_STATE SOSSI.D[5] E12 LCD.P[4] Z_STATE SOSSI.D[4] D14 LCD.P[3] Z_STATE SOSSI.D[3] C16 LCD.P[2] Z_STATE SOSSI.D[2] B16 LCD.P[1] Z_STATE SOSSI.D[1] A17 LCD.P[0] Z_STATE SOSSI.D[0] D15 LCD.HS Z_STATE SOSSI.CS
TYPE O Z I/O I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z O
MUX CTRL SETTING RegE[14:12] = 000 RegE[14:12] = 001 RegE[14:12] = 110 RegE[14:12] = 111 RegE[17:15] = 000 RegE[17:15] = 001 RegE[17:15] = 110 RegE[20:18] = 000 RegE[20:18] = 001 RegE[20:18] = 110 RegE[23:21] = 000 RegE[23:21] = 001 RegE[23:21] = 110 RegE[26:24] = 000 RegE[26:24] = 001 RegE[26:24] = 110 RegE[29:27] = 000 RegE[29:27] = 001 RegE[29:27] = 110 RegF[2:0] = 000 RegF[2:0] = 001 RegF[2:0] = 110 RegF[5:3] = 000 RegF[5:3] = 001 RegF[5:3] = 110 RegF[8:6] = 000 RegF[8:6] = 001 RegF[8:6] = 110 RegD[14:12] = 000 RegD[14:12] = 001 RegD[14:12] = 110
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
37
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. D16 SIGNAL NAME KB.C[4] GPIO27 E15 KB.C[3] GPIO63 B17 KB.C[2] GPIO61 C17 KB.C[1] MPUIO6 F14 KB.C[0] MPUIO0 F13 KB.R[4] MPUIO15 VLYNQ.TX1 D17 KB.R[3] MPUIO13 VLYNQ.TX0 E16 KB.R[2] MPUIO10 VLYNQ.CLK E17 KB.R[1] MPUIO9 VLYNQ.RX0 F15 KB.R[0] MPUIO8 VLYNQ.RX1 F17 KB.C[5] GPIO28 G13 MCBSP1.CLKS SOSSI.TE GPIO62 F16
TYPE O I/O O I/O O I/O O I/O O I/O I I/O O I I/O O I I/O I/O I I/O I I I/O I O I/O I I I/O I/O I/O
MUX CTRL SETTING Reg3[5:3] = 000 Reg3[5:3] = 111 Reg3[8:6] = 000 Reg3[8:6] = 111 Reg3[11:9] = 000 Reg3[11:9] = 111 Reg3[14:12] = 000 Reg3[14:12] = 001 Reg3[17:15] = 000 Reg3[17:15] = 001 Reg3[20:18] = 000 Reg3[20:18] = 001 Reg3[20:18] = 010 Reg3[23:21] = 000 Reg3[23:21] = 001 Reg3[23:21] = 010 Reg3[26:24] = 000 Reg3[26:24] = 001 Reg3[26:24] = 010 Reg3[29:27] = 000 Reg3[29:27] = 001 Reg3[29:27] = 010 Reg4[2:0] = 000 Reg4[2:0] = 001 Reg4[2:0] = 010 Reg3[2:0] = 000 Reg3[2:0] = 111 Reg4[8:6] = 000 Reg4[8:6] = 110 Reg4[8:6] = 111 Reg4[11:9] = 000 Reg4[11:9] = 111
PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# 0
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
A, F
0
A, F
0
A, F
0
A, F
0
A, F
Z
PRODUCT PREVIEW
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F
0
DVDD1 DVDD1
A, F
-
MCBSP1.CLKX GPIO54
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
38
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. G15 SIGNAL NAME MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 G14 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52 G17 H12 MCBSP1.DR GPIO51 CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 G16 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39 H14 H16 MPU_BOOT USB1.SUSP CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35 H15 CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD/SPI.DO GPIO34
TYPE I/O O O/Z I/O O I/O O/Z I/O I I/O O O O O I/O I O O I/O I O I O O I/O I/O I O O I/O I/O
MUX CTRL SETTING Reg4[14:12] = 000 Reg4[14:12] = 001 Reg4[14:12] = 010 Reg4[14:12] = 111 Reg4[17:15] = 000 Reg4[17:15] = 001 Reg4[17:15] = 010 Reg4[17:15] = 111 Reg4[20:18] = 000 Reg4[20:18] = 111 Reg4[23:21] = 000 Reg4[23:21] = 001 Reg4[23:21] = 010 Reg4[23:21] = 110 Reg4[23:21] = 111 Reg4[26:24] = 000 Reg4[26:24] = 001 Reg4[26:24] = 010 Reg4[26:24] = 111 Reg8[29:27] = 000 Reg8[29:27] = 010 Reg4[29:27] = 000 Reg4[29:27] = 001 Reg4[29:27] = 010 Reg4[29:27] = 011 Reg4[29:27] = 111 Reg5[2:0] = 000 Reg5[2:0] = 001 Reg5[2:0] = 010 Reg5[2:0] = 011 Reg5[2:0] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, F, G1
RESET STATE# Z
SUPPLY DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv)
A, F A, F, G1
LZ 0
DVDD1 DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
2 mA (Lv) 6 mA (Hv) PU20, PD20 4 mA (Lv) 11 mA (Hv)
A, F A, F
- Z DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
39
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. H17 SIGNAL NAME CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33 J11 CAM.D[4] ETM.D[4] UART3.TX GPIO32 H13 CAM.D[3] ETM.D[3] UART3.RX GPIO31 J14 CAM.D[2] ETM.D[2] UART3.CTS GPIO30 J16 CAM.D[1] ETM.D[1] UART3.RTS GPIO29 J17 CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3 J13 CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1
TYPE I O I I/O I O O I/O I O I I/O I O I I/O I O O I/O I O I/O I/O I O I/O I/O
MUX CTRL SETTING Reg5[5:3] = 000 Reg5[5:3] = 001 Reg5[5:3] = 010 Reg5[5:3] = 111 Reg5[8:6] = 000 Reg5[8:6] = 001 Reg5[8:6] = 010 Reg5[8:6] = 111 Reg5[11:9] = 000 Reg5[11:9] = 001 Reg5[11:9] = 010 Reg5[11:9] = 111 Reg5[14:12] = 000 Reg5[14:12] = 001 Reg5[14:12] = 010 Reg5[14:12] = 111 Reg5[17:15] = 000 Reg5[17:15] = 001 Reg5[17:15] = 010 Reg5[17:15] = 111 Reg5[20:18] = 000 Reg5[20:18] = 001 Reg5[20:18] = 010 Reg5[20:18] = 011 Reg5[23:21] = 000 Reg5[23:21] = 001 Reg5[23:21] = 010 Reg5[23:21] = 011
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
40
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. J12 SIGNAL NAME CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0/SPI.DI GPIO38 K12 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37 K17 LOW_STATE UART3.TX PWT UART2.TX TIMER.PWM0 GPIO50 K15 UART3.RX PWL UART2.RX TIMER.PWM1 GPIO49 K16 GPIO15 KB.R[7] TIMER.PWM2 VLYNQ.TX1 K14 GPIO14 KB.R[6] LCD.RED0 Z_STATE VLYNQ.TX0

TYPE I O I I/O I/O O O O O O I/O O O O O O I/O I O I O I/O I/O I O O I/O I O Z O
MUX CTRL SETTING Reg5[26:24] = 000 Reg5[26:24] = 001 Reg5[26:24] = 010 Reg5[26:24] = 011 Reg5[26:24] = 111 Reg5[29:27] = 000 Reg5[29:27] = 001 Reg5[29:27] = 010 Reg5[29:27] = 011 Reg5[29:27] = 110 Reg5[29:27] = 111 Reg6[2:0] = 000 Reg6[2:0] = 001 Reg6[2:0] = 010 Reg6[2:0] = 100 Reg6[2:0] = 110 Reg6[2:0] = 111 Reg6[5:3] = 000 Reg6[5:3] = 001 Reg6[5:3] = 011 Reg6[5:3] = 100 Reg6[5:3] = 111 Reg6[8:6] = 000 Reg6[8:6] = 001 Reg6[8:6] = 010 Reg6[8:6] = 100 Reg6[11:9] = 000 Reg6[11:9] = 001 Reg6[11:9] = 010 Reg6[11:9] = 011 Reg6[11:9] = 100
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
0
DVDD8
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
-
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
41
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. L17 SIGNAL NAME GPIO13 KB.R[5] LCD.BLUE0 Z_STATE VLYNQ.CLK L16 GPIO12 MCBSP3.FSX TIMER.EXTCLK VLYNQ.RX0 K13 GPIO11 HDQ VLYNQ.RX1 ETM.PSTAT[5] L15 GPIO7 MMC.DAT2 TCK MCSI1.CLK ETM.SYNC[1] L14 GPIO6 SPI.CS1 MCBSP3.ESX TIMER.EVENT3 MCSI1.DIN TMS M17 GPIO4 SPI.CS2 MCBSP3.FSX TIMER.EVENT4
TYPE I/O I O Z I/O I/O I/O I I I/O I/O I O I/O I/O I I/O O I/O O I/O I I I I/O O I/O I
MUX CTRL SETTING Reg6[14:12] = 000 Reg6[14:12] = 001 Reg6[14:12] = 010 Reg6[14:12] = 011 Reg6[14:12] = 100 Reg6[17:15] = 000 Reg6[17:15] = 001 Reg6[17:15] = 011 Reg6[17:15] = 100 Reg6[20:18] = 000 Reg6[20:18] = 001 Reg6[20:18] = 100 Reg6[20:18] = 101 Reg6[23:21] = 000 Reg6[23:21] = 001 Reg6[23:21] = 011 Reg6[23:21] = 100 Reg6[23:21] = 101 Reg6[26:24] = 000 Reg6[26:24] = 001 Reg6[26:24] = 010 Reg6[26:24] = 011 Reg6[26:24] = 100 Reg6[26:24] = 101 Reg6[29:27] = 000 Reg6[29:27] = 001 Reg6[29:27] = 010 Reg6[29:27] = 011
PULLUP/ PULLDN PU100, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
42
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. L13 SIGNAL NAME GPIO3 SPI.CS3 MCBSP3.FSX LED1 ETM.PSTAT[3] M16 GPIO2 SPI.CLK ETM.PSTAT[4] M15 N17 GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS SPIF.DOUT MMC2.CLKIN N16 MPUIO5 LOW_PWR UART3.RTS UART1.DTR M14 MPUIO4 EXT_DMA_REQ1 LED2 UWIRE.CS2 SPIF.CS2 MCBSP3.DR L12 MPUIO2 EXT_DMA_REQ0 UWIRE.CS1 SPIF.CS1 N14
TYPE I/O O I/O O O I/O O O I/O O I/O I I O I I/O O O O I/O I O O O I I/O I O O I I/O
MUX CTRL SETTING Reg7[2:0] = 000 Reg7[2:0] = 001 Reg7[2:0] = 010 Reg7[2:0] = 011 Reg7[2:0] = 101 Reg7[5:3] = 000 Reg7[5:3] = 001 Reg7[5:3] = 101 Reg7[8:6] = 000 Reg7[8:6] = 001 Reg7[11:9] = 000 Reg7[11:9] = 001 Reg7[11:9] = 010 Reg7[11:9] = 011 Reg7[11:9] = 110 Reg7[14:12] = 000 Reg7[14:12] = 001 Reg7[14:12] = 011 Reg7[14:12] = 100 Reg7[17:15] = 000 Reg7[17:15] = 001 Reg7[17:15] = 010 Reg7[17:15] = 011 Reg7[17:15] = 100 Reg7[17:15] = 110 Reg7[20:18] = 000 Reg7[20:18] = 001 Reg7[20:18] = 010 Reg7[20:18] = 110 Reg9[8:6] = 000 Reg9[8:6] = 110
PULLUP/ PULLDN PU100, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 2 mA (Lv) 6 mA (Hv)
A, F, G1 A, F, G1
LZ LZ
DVDD9 DVDD9
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F
LZ
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
MPU_RST MPUIO14
2 mA (Lv) 6 mA (Hv)
A, F
-
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
43
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. N15 SIGNAL NAME MPUIO1 RTCK SPIF.SCK P16 M11 P14 I2C.SCL I2C.SDA GPIO48 UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR SPIF.DIN GPIO47 TYPE I/O I/O I/O I/O/Z I/O/Z I I O I I I/O I/O O O O O O O/Z I/O I/O O O I/O I Z O I/O O I/O I/O MUX CTRL SETTING Reg7[23:21] = 000 Reg7[23:21] = 001 Reg7[23:21] = 110 Reg7[26:24] = 000 Reg7[29:27] = 000 Reg7[29:27] = 111 Reg8[2:0] = 000 Reg8[2:0] = 001 Reg8[2:0] = 010 Reg8[2:0] = 011 Reg8[2:0] = 110 Reg8[2:0] = 111 Reg8[5:3] = 000 Reg8[5:3] = 001 Reg8[5:3] = 010 Reg8[5:3] = 011 Reg8[5:3] = 100 Reg8[5:3] = 101 Reg8[5:3] = 110 Reg8[5:3] = 111 Reg8[8:6] = 000 Reg8[8:6] = 001 Reg8[8:6] = 010 Reg8[8:6] = 100 Reg8[11:9] = 000 Reg8[11:9] = 001 Reg8[11:9] = 010 Reg8[11:9] = 100 Reg8[11:9] = 110 Reg8[11:9] = 111 PU100, PD20 4 mA (Lv) 8 mA (Hv) A, F Z DVDD9 PU20, PD20 4 mA (Lv) 8 mA (Hv) A, F, G1 0 DVDD9 PU20, PD20 4 mA (Lv) 8 mA (Hv) A, F, G1 0 DVDD9 PU20, PD20 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv) D D A, F Z Z LZ DVDD9 DVDD9 DVDD9 PULLUP/ PULLDN PU100, PD20 BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv) OTHER A, F RESET STATE# Z SUPPLY DVDD9
PRODUCT PREVIEW
R15
UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UART3.RTS MCBSP3.DXZ SPIF.DOUT GPIO46
P15
UWIRE.SCLK KB.C[7] MPUIO1 UART3.CTS
R17
Z_STATE UWIRE.CS0 MCBSP3.CLKX UART3.TX SPIF.CS0 GPIO45

I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
44
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. R16 SIGNAL NAME Z_STATE UWIRE.CS3 KB.C[6] SPIF.CS3 UART3.RX Z_STATE GPIO44 T17 BFAIL/EXT_FIQ UART3.CTS UART1.DSR MMC2.DATDIR1 N12 R14 U17 T15 M10 P13 R13 U16 N11 T14

TYPE Z O O O I Z I/O I I I O O I/O I I O TBD I I I I/O I/O I/O
MUX CTRL SETTING Reg8[14:12] = 000 Reg8[14:12] = 001 Reg8[14:12] = 010 Reg8[14:12] = 011 Reg8[14:12] = 100 Reg8[14:12] = 110 Reg8[14:12] = 111 Reg8[17:15] = 000 Reg8[17:15] = 001 Reg8[17:15] = 010 Reg8[17:15] = 110 Reg9[11:9] = 000 Reg9[11:9] = 111 NA NA NA TBD NA NA NA NA NA NA
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
Z
DVDD9
RST_OUT GPIO41 CONF TDI TDO VLYNQ.TX0 TMS TCK TRST EMU0 EMU1 RTCK
PU20, PD20 PU20, PD20 PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F A A
0 LZ LZ -
DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9
4 mA (Lv) 8 mA (Hv) PD100, PU20 PD100, PU20 PU20, PD20 PU100, PD20 PU100, PD20 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 11 mA (Hv) A A A A A A
LZ LZ - Input Input -
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
45
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. N10 SIGNAL NAME MCSI1.SYNC MCBSP3.DR USB1.VP MCBSP3.FSX U15 MCSI1.CLK MCBSP3.DX USB1.VM TDI MCBSP3.CLKX GPIO43 U14 Z_STATE MCBSP3.CLKX USB1.TXEN MCSI1.DIN Z_STATE GPIO42 P12 MCSI1.DIN USB1.RCV EMU1 MCBSP3.DR SSI.ACWAKE GPIO56 R12 BCLKREQ UART3.CTS MMC2.DAT2 GPIO40 L10 BCLK UART3.RTS CAM.OUTCLK GPIO17
TYPE I/O I I I/O I/O O I I I/O I/O Z I/O O I Z I/O I I I/O I O I/O I I I/O I/O O O O I/O
MUX CTRL SETTING RegA[5:3] = 000 RegA[5:3] = 001 RegA[5:3] = 010 RegA[5:3] = 100 RegA[8:6] = 000 RegA[5:3] = 001 RegA[5:3] = 010 RegA[5:3] = 011 RegA[5:3] = 100 RegA[5:3] = 111 Reg9[5:3] = 000 Reg9[5:3] = 001 Reg9[5:3] = 010 Reg9[5:3] = 100 Reg9[5:3] = 110 Reg9[5:3] = 111 RegA[11:9] = 000 RegA[11:9] = 001 RegA[11:9] = 011 RegA[11:9] = 100 RegA[11:9] = 110 RegA[11:9] = 111 Reg9[29:27] = 000 Reg9[29:27] = 001 Reg9[29:27] = 110 Reg9[29:27] = 111 RegA[2:0] = 000 RegA[2:0] = 001 RegA[2:0] = 110 RegA[2:0] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD7
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
Z
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD7
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
46
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. R11 SIGNAL NAME LOW_STATE UART1.RTS UART1.IRSHDN Z_STATE GPIO39 M9 UART1.CTS UART1.IRSEL GPIO38 U13 UART1.RX UART1.IRRX GPIO37 T12 LOW_STATE UART1.TX UART1.IRTX CCP.DATAM P11 MCSI1.DOUT USB1.TXD TDO MCBSP3.DX CCP.DATAP GPIO18 U12 CLK32K_OUT MPUIO0 USB1.SPEED UART1.TX GPIO36 U11 U10
TYPE O O O Z I/O I O I/O I I I/O O O O I O O O O I I/O O I/O O O I/O - -
MUX CTRL SETTING Reg9[14:12] = 000 Reg9[14:12] = 001 Reg9[14:12] = 010 Reg9[14:12] = 110 Reg9[14:12] = 111 Reg9[17:15] = 000 Reg9[17:15] = 010 Reg9[17:15] = 111 Reg9[20:18] = 000 Reg9[20:18] = 010 Reg9[20:18] = 111 Reg9[23:21] = 000 Reg9[23:21] = 001 Reg9[23:21] = 010 Reg9[23:21] = 110 Reg9[26:24] = 000 Reg9[26:24] = 001 Reg9[26:24] = 011 Reg9[26:24] = 100 Reg9[26:24] = 110 Reg9[26:24] = 111 RegA[14:12] = 000 RegA[14:12] = 100 RegA[14:12] = 101 RegA[14:12] = 110 RegA[14:12] = 111 NA NA
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
2 mA (Lv) 6 mA (Hv)
A, B, F, G1
0
DVDD7
2 mA (Lv) 6 mA (Hv)
A, B, F, G1, H3
0
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A
U
DVDDRTC
OSC32K_IN OSC32K_OUT
E E
NA NA
NA NA
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
47
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. N9 SIGNAL NAME RTC_WAKE_INT USB1.SE0 RST_HOST_OUT CCP.CLKM GPIO55 P10 RTC_ON_NOFF CCP.CLKP T11 N8 P9 CLK32K_IN PWRON_RESET MMC.DAT3 MPUIO9 MPUIO6 CFLASH.CD1 SSI.ACFLAG M8 MMC.CLK SSI.CARDY GPIO57 R8 MMC.DAT0/SPI.DI Z_STATE CFLASH.IOIS16 SSI.ACRDY GPIO58 T9 MMC.DAT2 Z_STATE MPUIO11 CFLASH.RFSFT SSI.CAFLAG U9 MMC.DAT1 MPUIO10 MPUIO7 CFLASH.IRFQ SSI.ACDATA
TYPE O O O I I/O I I I I I/O I/O I/O I O O I I/O I/O Z I O I/O I/O Z I/O O I I/O I/O I/O I O
MUX CTRL SETTING Reg9[2:0] = 000 Reg9[2:0] = 100 Reg9[2:0] = 101 Reg9[2:0] = 110 Reg9[2:0] = 111 Reg8[20:18] = 000 Reg8[20:18] = 110 RegA[17:15] = 000 NA Reg10[17:15] = 000 Reg10[17:15] = 001 Reg10[17:15] = 010 Reg10[17:15] = 011 Reg10[17:15] = 110 RegA[23:21] = 000 RegA[23:21] = 101 RegA[23:21] = 110 RegB[2:0] = 000 RegB[2:0] = 001 RegB[2:0] = 011 RegB[2:0] = 110 RegB[2:0] = 111 RegA[20:18] = 000 RegA[20:18] = 001 RegA[20:18] = 010 RegA[20:18] = 011 RegA[20:18] = 110 RegA[26:24] = 000 RegA[26:24] = 001 RegA[26:24] = 010 RegA[26:24] = 011 RegA[26:24] = 110
PULLUP/ PULLDN
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, B
RESET STATE# 0
SUPPLY DVDDRTC
2 mA (Lv) 6 mA (Hv)
A, B, G1
Z
DVDDRTC DVDDRTC DVDDRTC DVDD6
A A PU20, PD20 4 mA (Lv) 8 mA (Hv) A, F, G1
Input Input Z
PRODUCT PREVIEW
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
48
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. N7 SIGNAL NAME MMC.CMD/SPI.DO CFLASH.CD2 SSI.CADATA GPIO55 P8 MCSI2.CLK USB2.SUSP USB0.SUSP MMC2.CLK GPIO27 R7 MCSI2.DIN USB2.VP USB0.VP GPIO26 T8 MCSI2.DOUT USB2.TXEN USB0.TXEN Z_STATE GPIO25 U8 MCSI2.SYNC GPIO7 USB2.SPEED USB0.SPEED MMC2.CMDDIR T7 MCLKREQ EXT_MASTER_REQ UART2.RX MMC2.DAT3 GPIO23 U7 GPIO9 EMU0 MCSI1.SYNC MMC2.DAT0/SPI.DI
TYPE I/O I I I/O I/O O O O I/O I I I I/O O O O Z I/O I/O I/O O O O I O I I/O I/O I/O I/O I/O I/O
MUX CTRL SETTING RegA[29:27] = 000 RegA[29:27] = 011 RegA[29:27] = 110 RegA[29:27] = 111 RegB[5:3] = 000 RegB[5:3] = 001 RegB[5:3] = 101 RegB[5:3] = 110 RegB[5:3] = 111 RegB[8:6] = 000 RegB[8:6] = 001 RegB[8:6] = 101 RegB[8:6] = 111 RegB[11:9] = 000 RegB[11:9] = 001 RegB[11:9] = 101 RegB[11:9] = 110 RegB[11:9] = 111 RegB[14:12] = 000 RegB[14:12] = 001 RegB[14:12] = 010 RegB[14:12] = 110 RegB[14:12] = 111 RegB[20:18] = 000 RegB[20:18] = 001 RegB[20:18] = 010 RegB[20:18] = 110 RegB[20:18] = 111 RegB[23:21] = 000 RegB[23:21] = 011 RegB[23:21] = 100 RegB[23:21] = 110
PULLUP/ PULLDN PD100, PU20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# Z
SUPPLY DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G2
0
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G3
LZ
DVDD3
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
49
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. P7 SIGNAL NAME GPIO8 TRST MCSI1.DOUT MMC2.CMD/SPI.DO R6 L8 MPUIO3 MMC2.DAT1 MCBSP2.DR MCBSP2.DX MCBSP2.DXZ GPIO22 N6 MCBSP2.FSX VLYNQ.RX1 GPIO21 U6 MCBSP2.CLKR GPIO11 VLYNQ.CLK U5 MCBSP2.CLKX VLYNQ.TX1 GPIO20 R5 MCBSP2.FSR GPIO12 VLYNQ.RX0 T5 MCBSP2.DX MCBSP2.DR MCBSP2.DXZ VLYNQ.TX0 GPIO19 U4 UART2.RX USB2.VM USB0.VM GPIO18
TYPE I/O I O I/O I/O I/O I O O/Z I/O I/O I I/O I/O I/O I/O I/O O I/O I/O I/O I O I O/Z O I/O I I I I/O
MUX CTRL SETTING RegB[26:24] = 000 RegB[26:24] = 011 RegB[26:24] = 100 RegB[26:24] = 110 RegB[29:27] = 000 RegB[29:27] = 110 RegC[2:0] = 000 RegC[2:0] = 001 RegC[2:0] = 010 RegC[2:0] = 111 RegC[5:3] = 000 RegC[5:3] = 011 RegC[5:3] = 111 RegC[8:6] = 000 RegC[8:6] = 001 RegC[8:6] = 011 RegC[11:9] = 000 RegC[11:9] = 011 RegC[11:9] = 111 RegC[14:12] = 000 RegC[14:12] = 001 RegC[14:12] = 011 RegC[17:15] = 000 RegC[17:15] = 001 RegC[17:15] = 010 RegC[17:15] = 011 RegC[17:15] = 111 RegC[20:18] = 000 RegC[20:18] = 001 RegC[20:18] = 101 RegC[20:18] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G3
RESET STATE# LZ
SUPPLY DVDD3
PU20, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F, G1 A, F, G2
LZ LZ
DVDD3 DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
LZ
DVDD3
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
LZ
DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
0
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
50
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. P6 SIGNAL NAME UART2.CTS USB2.RCV GPIO7 USB0.RCV T4 LOW_STATE UART2.RTS USB2.SE0 MPUIO5 MPUIO12 USB0.SE0 LOW_STATE R4 LOW_STATE UART2.TX USB2.TXD USB0.TXD Z_STATE GPIO17 P5 UART2.BCLK SYS_CLK_IN U3 MCLK MMC2.DATDIR0 GPIO24 P4 USB.PUEN USB.CLKO USB.PUDIS Z_STATE LOW_POWER GPIO58 T2 USB.DP I2C.SDA UART1.RX USB.PUEN
TYPE I I I/O I O O O I/O I/O O O O O O O Z I/O O I O O I/O O O O Z O I/O I/O I/O/Z I O
MUX CTRL SETTING RegC[23:21] = 000 RegC[23:21] = 001 RegC[23:21] = 010 RegC[23:21] = 101 RegC[26:24] = 000 RegC[26:24] = 001 RegC[26:24] = 010 RegC[26:24] = 011 RegC[26:24] = 100 RegC[26:24] = 101 RegC[26:24] = 110 RegC[29:27] = 000 RegC[29:27] = 001 RegC[29:27] = 010 RegC[29:27] = 101 RegC[29:27] = 110 RegC[29:27] = 111 RegD[2:0] = 000 RegD[2:0] = 110 RegB[17:15] = 000 RegB[17:15] = 110 RegB[17:15] = 111 RegD[5:3] = 000 RegD[5:3] = 001 RegD[5:3] = 011 RegD[5:3] = 100 RegD[5:3] = 110 RegD[5:3] = 111 USBTCTL[6:4] = 000 USBTCTL[6:4] = 100 USBTCTL[6:4] = 101 USBTCTL[6:4] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F
RESET STATE# LZ
SUPPLY DVDD3
4 mA (Lv) 8 mA (Hv)
A, F, G2
0
DVDD3
4 mA (Lv) 8 mA (Hv) PU20, PD20 4 mA (Lv) 8 mA (Hv)
A, F, G2
0
DVDD3 DVDD3
A, F, G1
0
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
1
DVDD2
18.3 mA (in USB mode)
C
Z
DVDD2
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
51
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G2
0
DVDD3
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. U1 SIGNAL NAME USB.DM I2C.SCL UART1.TX Z_STATE R2 P2 T1 OSC1_IN OSC1_OUT FLASH.CS1U GPIO16 R3 P3 N3 FLASH.WP FLASH.WE FLASH.RP FLASH.CS2UWE M5 FLASH.OE FLASH.A[25:17] F3 J4 J2 H2 H5 F4 H4 C1 G6 G5 G2 G4 G3 F5 F1

TYPE I/O I/O/Z O Z I O O I/O O O O O O O
MUX CTRL SETTING
PULLUP/ PULLDN
BUFFER STRENGTH 18.3 mA (in USB mode)
OTHER C
RESET STATE# Z
SUPPLY DVDD2
USBTCTL[6:4] = 100 USBTCTL[6:4] = 101 USBTCTL[6:4] = 111 NA NA RegA[2:0] = 000 RegA[2:0] = 111 NA NA RegF[23:21] = 000 RegF[23:21] = 001 NA NA
E E 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) A, F
NA NA 1
NA NA DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
A A A
0 1 0
PRODUCT PREVIEW
A A, G1
1 0
FLASH.A[16] FLASH.A[15] FLASH.A[14] FLASH.A[13] FLASH.A[12] FLASH.A[11]
O O O O O O
Reg11[5:3] = 000 Reg11[8:6] = 000 Reg11[11:9] = 000 Reg11[14:12] = 000 Reg11[17:15] = 000 Reg11[20:18] = 000
PU20, PD20
4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
A, G1 A, G1 A, G1 A, G1 A, G1 A, G1
0 0 0 1 0 0
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
52
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. F2 E1 D1 E2 C1 D2 E3 E4 C2 D3 N4 R1 P1 K7 M3 M4 N2 L5 N1 K6 L4 M2 J7 L2 M1 L1 K1 FLASH.CLK FLASH.CS2UOE L6 FLASH.RDY GPIO10 H6

SIGNAL NAME FLASH.A[10] FLASH.A[9] FLASH.A[8] FLASH.A[7] FLASH.A[6] FLASH.A[5] FLASH.A[4] FLASH.A[3] FLASH.A[2] FLASH.A[1] FLASH.D[15:0]
TYPE O O O O O O O O O O I/O
MUX CTRL SETTING Reg11[23:21] = 000 Reg11[26:24] = 000 Reg12[5:3] = 000 Reg12[8:6] = 000 Reg12[11:9] = 000 Reg12[14:12] = 000 Reg12[17:15] = 000 Reg12[20:18] = 000 Reg12[23:21] = 000 Reg12[26:24] = 000 NA
PULLUP/ PULLDN
BUFFER STRENGTH 3 mA (Lv) 8 mA (Hv)
OTHER A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, K
RESET STATE# 0 0 0 0 0 0 0 0 0 0 0
SUPPLY DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv)
O O I I/O O
Reg10[23:21] = 000 Reg10[23:21] = 001 RegF[29:27] = 000 RegF[29:27] = 001 NA PU100, PD20
3 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, K, G1
0
DVDD5 DVDD5 DVDD5
A, F
Input
FLASH.ADV
A
1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
53
PRODUCT PREVIEW
Introduction
Table 2-3. ZDY Package Terminal Characteristics (Continued)
ZDY BALL NO. J8 SIGNAL NAME FLASH.CS2 FLASH.BAA FLASH.CS2L J5 J3 K3 J1 GPIO62 FLASH.CS0 FLASH.CS1 FLASH.CS1L FLASH.CS2U GPIO5 FLASH.BE[0] FLASH.CS2UOE GPIO59 K2 FLASH.BE[1] FLASH.CS2UWE GPIO60 J6
TYPE O O O I/O O O O O I/O O O I/O O O I/O O I/O
MUX CTRL SETTING RegD[8:6] = 000 RegD[8:6] = 000 RegD[8:6] = 000 Reg10[2:0] = 000 Reg10[2:0] = 001 Reg10[29:27] = 000 Reg10[29:27] = 001 Reg10[20:18] = 000 Reg10[20:18] = 001 Reg10[8:6] = 000 Reg10[8:6] = 001 Reg10[8:6] = 111 Reg10[5:3] = 000 Reg10[5:3] = 001 Reg10[5:3] = 111 Reg10[26:24] = 000 Reg10[26:24] = 111
PULLUP/ PULLDN
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A
RESET STATE# 1
SUPPLY DVDD5
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F, G1 A A, F A, F
Input 1 1 0
DVDD5 DVDD5 DVDD5 DVDD5
PRODUCT PREVIEW
4 mA (Lv) 8 mA (Hv)
A, F
0
DVDD5
FLASH.CS3 GPIO3
4 mA (Lv) 8 mA (Hv)
A, F
1
DVDD5
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
54
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics
ZZG BALL NO. G8 C14 D4 B4 H7 C8 D10 H8 H11 H9 H10 B8 B12 G9 G11 G12 B9 G10 A1 B6 B2 A2 C3 B3 C12 D12 D13 C11 C13 D11 D14 C10 D8 C4 C7 D5 D7 C5 C6 D6

SIGNAL NAME
TYPE
MUX CTRL SETTING
PULLUP/ PULLDN
BUFFER STRENGTH 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
OTHER
RESET STATE# 1 0 0 1 1 0 0 1 0
SUPPLY
SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU SDRAM.WE SDRAM.A[13:0]
O I/O I/O O O O O O O
NA NA NA NA NA NA NA NA NA
A A, K A, K A A A, K A, K A A
DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
O I/O
NA NA
3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv)
A A, K
0 0
DVDD4 DVDD4
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
55
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. C9 D9 H12 B15 SIGNAL NAME SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE SOSSI.CMD C15 LCD.PCLK Z_STATE SOSSI.WR TYPE O O O O O Z O O Z O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O O Z I/O I/O MUX CTRL SETTING NA NA NA RegD[11:9] = 000 RegD[11:9] = 001 RegD[11:9] = 010 RegD[11:9] = 110 RegD[17:15] = 000 RegD[17:15] = 001 RegD[17:15] = 110 RegD[20:18] = 000 RegD[20:18] = 001 RegD[20:18] = 110 RegD[20:18] = 111 RegD[23:21] = 000 RegD[23:21] = 001 RegD[23:21] = 110 RegD[23:21] = 111 RegD[26:24] = 000 RegD[26:24] = 001 RegD[26:24] = 110 RegD[26:24] = 111 RegD[29:27] = 000 RegD[29:27] = 001 RegD[29:27] = 110 RegD[29:27] = 111 RegE[2:0] = 000 RegE[2:0] = 001 RegE[2:0] = 110 RegE[2:0] = 111 PU20, PD20 2 mA (Lv) 6 mA (Hv) A, F, G1 0 DVDD1 PU20, PD20 2 mA (Lv) 6 mA (Hv) A, F, G1 0 DVDD1 PU20, PD20 2 mA (Lv) 6 mA (Hv) F, A, G1 0 DVDD1 PU20, PD20 2 mA (Lv) 6 mA (Hv) A, F, G1 0 DVDD1 PU20, PD20 2 mA (Lv) 6 mA (Hv) A, F, G1 0 DVDD1 2 mA (Lv) 6 mA (Hv) A, F, G1 0 DVDD1 PULLUP/ PULLDN BUFFER STRENGTH 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 6 mA (Hv) 3 mA (Lv) 8 mA (Hv) 2 mA (Lv) 6 mA (Hv) OTHER A, K A, K A A, F, G1 RESET STATE# U 0 1 0 SUPPLY DVDD4 DVDD4 DVDD4 DVDD1
PRODUCT PREVIEW
D15
LCD.P[15] Z_STATE SOSSI.D[15] GPIO2
C16
LCD.P[14] Z_STATE SOSSI.D[14] GPIO35
A17
LCD.P[13] Z_STATE SOSSI.D[13] GPIO34
G13
LCD.P[12] Z_STATE SOSSI.D[12] GPIO33
B17
LCD.P[11] Z_STATE SOSSI.D[11] GPIO32
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
56
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. C17 SIGNAL NAME LCD.P[10] Z_STATE SOSSI.D[10] GPIO31 D16 LCD.P[9] Z_STATE SOSSI.D[9] GPIO30 B18 LCD.VS Z_STATE SOSSI.RD D17 LCD.P[8] Z_STATE SOSSI.D[8] GPIO29 C18 LCD.P[7] Z_STATE SOSSI.D[7] B19 LCD.P[6] Z_STATE SOSSI.D[6] A20 LCD.P[5] Z_STATE SOSSI.D[5] H13 LCD.P[4] Z_STATE SOSSI.D[4] G14 LCD.P[3] Z_STATE SOSSI.D[3]
TYPE O Z I/O I/O O Z I/O I/O O Z O O Z I/O I/O O Z I/O O Z I/O O Z I/O O Z I/O O Z I/O
MUX CTRL SETTING RegE[5:3] = 000 RegE[5:3] = 001 RegE[5:3] = 110 RegE[5:3] = 111 RegE[8:6] = 000 RegE[8:6] = 001 RegE[8:6] = 110 RegE[8:6] = 111 RegE[11:9] = 000 RegE[11:9] = 001 RegE[11:9] = 110 RegE[14:12] = 000 RegE[14:12] = 001 RegE[14:12] = 110 RegE[14:12] = 111 RegE[17:15] = 000 RegE[17:15] = 001 RegE[17:15] = 110 RegE[20:18] = 000 RegE[20:18] = 001 RegE[20:18] = 110 RegE[23:21] = 000 RegE[23:21] = 001 RegE[23:21] = 110 RegE[26:24] = 000 RegE[26:24] = 001 RegE[26:24] = 110 RegE[29:27] = 000 RegE[29:27] = 001 RegE[29:27] = 110
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
57
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. C19 SIGNAL NAME LCD.P[2] Z_STATE SOSSI.D[2] B21 LCD.P[1] Z_STATE SOSSI.D[1] D18 LCD.P[0] Z_STATE SOSSI.D[0] C20 LCD.HS Z_STATE SOSSI.CS C21 E18 D19 D20 F18 E19 KB.C[4] GPIO27 KB.C[3] GPIO63 KB.C[2] GPIO61 KB.C[1] MPUIO6 KB.C[0] MPUIO0 KB.R[4] MPUIO15 VLYNQ.TX1 E20 KB.R[3] MPUIO13 VLYNQ.TX0 H14 KB.R[2] MPUIO10 VLYNQ.CLK
TYPE O Z I/O O Z I/O O Z I/O O Z O O I/O O I/O O I/O O I/O O I/O I I/O O I I/O O I I/O I/O
MUX CTRL SETTING RegF[2:0] = 000 RegF[2:0] = 001 RegF[2:0] = 110 RegF[5:3] = 000 RegF[5:3] = 001 RegF[5:3] = 110 RegF[8:6] = 000 RegF[8:6] = 001 RegF[8:6] = 110 RegD[14:12] = 000 RegD[14:12] = 001 RegD[14:12] = 110 Reg3[5:3] = 000 Reg3[5:3] = 111 Reg3[8:6] = 000 Reg3[8:6] = 111 Reg3[11:9] = 000 Reg3[11:9] = 111 Reg3[14:12] = 000 Reg3[14:12] = 001 Reg3[17:15] = 000 Reg3[17:15] = 001 Reg3[20:18] = 000 Reg3[20:18] = 001 Reg3[20:18] = 010 Reg3[23:21] = 000 Reg3[23:21] = 001 Reg3[23:21] = 010 Reg3[26:24] = 000 Reg3[26:24] = 001 Reg3[26:24] = 010
PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD1
PRODUCT PREVIEW
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20
2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv)
A, F A, F A, F A, F A, F A, F
0 0 0 0 0 Z
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
58
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. F19 SIGNAL NAME KB.R[1] MPUIO9 VLYNQ.RX0 G18 KB.R[0] MPUIO8 VLYNQ.RX1 G19 KB.C[5] GPIO28 G20 MCBSP1.CLKS SOSSI.TE GPIO62 G21 MCBSP1.CLKX GPIO54 H15 MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 H18 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52 H20 MCBSP1.DR GPIO51 H19 CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 J15 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39
TYPE I I/O I I I/O I O I/O I I I/O I/O I/O I/O O O/Z I/O O I/O O/Z I/O I I/O O O O O I/O I O O I/O
MUX CTRL SETTING Reg3[29:27] = 000 Reg3[29:27] = 001 Reg3[29:27] = 010 Reg4[2:0] = 000 Reg4[2:0] = 001 Reg4[2:0] = 010 Reg3[2:0] = 000 Reg3[2:0] = 111 Reg4[8:6] = 000 Reg4[8:6] = 110 Reg4[8:6] = 111 Reg4[11:9] = 000 Reg4[11:9] = 111 Reg4[14:12] = 000 Reg4[14:12] = 001 Reg4[14:12] = 010 Reg4[14:12] = 111 Reg4[17:15] = 000 Reg4[17:15] = 001 Reg4[17:15] = 010 Reg4[17:15] = 111 Reg4[20:18] = 000 Reg4[20:18] = 111 Reg4[23:21] = 000 Reg4[23:21] = 001 Reg4[23:21] = 010 Reg4[23:21] = 110 Reg4[23:21] = 111 Reg4[26:24] = 000 Reg4[26:24] = 001 Reg4[26:24] = 010 Reg4[26:24] = 111
PULLUP/ PULLDN PU100, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD1
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F
0
DVDD1 DVDD1
A, F
-
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
Z
DVDD1
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F, G1
0
DVDD1
PU20, PD20 PU20, PD20
2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv)
A, F
LZ
DVDD1 DVDD8
A, F, G1
0
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
59
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD1
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. J20 SIGNAL NAME MPU_BOOT USB1.SUSP J18 CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35 J19 CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD/SPI.DO GPIO34 TYPE I O I O O I/O I/O I O O I/O I/O I O I I/O I O O I/O I O I I/O I O I I/O I O O I/O MUX CTRL SETTING Reg8[29:27] = 000 Reg8[29:27] = 010 Reg4[29:27] = 000 Reg4[29:27] = 001 Reg4[29:27] = 010 Reg4[29:27] = 011 Reg4[29:27] = 111 Reg5[2:0] = 000 Reg5[2:0] = 001 Reg5[2:0] = 010 Reg5[2:0] = 011 Reg5[2:0] = 111 Reg5[5:3] = 000 Reg5[5:3] = 001 Reg5[5:3] = 010 Reg5[5:3] = 111 Reg5[8:6] = 000 Reg5[8:6] = 001 Reg5[8:6] = 010 Reg5[8:6] = 111 Reg5[11:9] = 000 Reg5[11:9] = 001 Reg5[11:9] = 010 Reg5[11:9] = 111 Reg5[14:12] = 000 Reg5[14:12] = 001 Reg5[14:12] = 010 Reg5[14:12] = 111 Reg5[17:15] = 000 Reg5[17:15] = 001 Reg5[17:15] = 010 Reg5[17:15] = 111 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 4 mA (Lv) 11 mA (Hv) A, F Z DVDD8 PU20, PD20 PULLUP/ PULLDN BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv) 4 mA (Lv) 11 mA (Hv) OTHER A, F RESET STATE# - SUPPLY
A, F
Z
DVDD8
PRODUCT PREVIEW
J14
CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33
K18
CAM.D[4] ETM.D[4] UART3.TX GPIO32
K19
CAM.D[3] ETM.D[3] UART3.RX GPIO31
K15
CAM.D[2] ETM.D[2] UART3.CTS GPIO30
K14
CAM.D[1] ETM.D[1] UART3.RTS GPIO29
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
60
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. L19 SIGNAL NAME CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3 L18 CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1 L15 CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0/SPI.DI GPIO38 M19 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37 M18 LOW_STATE UART3.TX PWT UART2.TX TIMER.PWM0 GPIO50 L14 UART3.RX PWL UART2.RX TIMER.PWM1 GPIO49
TYPE I O I/O I/O I O I/O I/O I O I I/O I/O O O O O O I/O O O O O O I/O I O I O I/O
MUX CTRL SETTING Reg5[20:18] = 000 Reg5[20:18] = 001 Reg5[20:18] = 010 Reg5[20:18] = 011 Reg5[23:21] = 000 Reg5[23:21] = 001 Reg5[23:21] = 010 Reg5[23:21] = 011 Reg5[26:24] = 000 Reg5[26:24] = 001 Reg5[26:24] = 010 Reg5[26:24] = 011 Reg5[29:27] = 000 Reg5[29:27] = 001 Reg5[29:27] = 010 Reg5[29:27] = 011 Reg5[29:27] = 110 Reg5[29:27] = 111 Reg6[2:0] = 000 Reg6[2:0] = 001 Reg6[2:0] = 010 Reg6[2:0] = 100 Reg6[2:0] = 110 Reg6[2:0] = 111 Reg6[5:3] = 000 Reg6[5:3] = 001 Reg6[5:3] = 011 Reg6[5:3] = 100 Reg6[5:3] = 111 Reg5[26:24] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD8
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
0
DVDD8
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
-
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
61
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. M20 SIGNAL NAME GPIO15 KB.R[7] TIMER.PWM2 VLYNQ.TX1 N21 GPIO14 KB.R[6] LCD.RED0 Z_STATE VLYNQ.TX0 N19 GPIO13 KB.R[5] LCD.BLUE0 Z_STATE VLYNQ.CLK N18 GPIO12 MCBSP3.FSX TIMER.EXTCLK VLYNQ.RX0 N20 GPIO11 HDQ VLYNQ.RX1 ETM.PSTAT[5] M15 GPIO7 MMC.DAT2 TCK MCSI1.CLK ETM.SYNC[1]

TYPE I/O I O O I/O I O Z O I/O I O Z I/O I/O I/O I I I/O I/O I O I/O I/O I I/O O
MUX CTRL SETTING Reg6[8:6] = 000 Reg6[8:6] = 001 Reg6[8:6] = 010 Reg6[8:6] = 100 Reg6[11:9] = 000 Reg6[11:9] = 001 Reg6[11:9] = 010 Reg6[11:9] = 011 Reg6[11:9] = 100 Reg6[14:12] = 000 Reg6[14:12] = 001 Reg6[14:12] = 010 Reg6[14:12] = 011 Reg6[14:12] = 100 Reg6[17:15] = 000 Reg6[17:15] = 001 Reg6[17:15] = 011 Reg6[17:15] = 100 Reg6[20:18] = 000 Reg6[20:18] = 001 Reg6[20:18] = 100 Reg6[20:18] = 101 Reg6[23:21] = 000 Reg6[23:21] = 001 Reg6[23:21] = 011 Reg6[23:21] = 100 Reg6[23:21] = 101
PULLUP/ PULLDN PU100, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
62
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. P19 SIGNAL NAME GPIO6 SPI.CS1 MCBSP3.ESX TIMER.EVENT3 MCSI1.DIN TMS P20 GPIO4 SPI.CS2 MCBSP3.FSX TIMER.EVENT4 P18 GPIO3 SPI.CS3 MCBSP3.FSX LED1 ETM.PSTAT[3] M14 GPIO2 SPI.CLK ETM.PSTAT[4] R19 R18 GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS SPIF.DOUT MMC2.CLKIN T20 MPUIO5 LOW_PWR UART3.RTS UART1.DTR

TYPE I/O O I/O I I I I/O O I/O I I/O O I/O O O I/O O O I/O O I/O I I O I I/O O O O
MUX CTRL SETTING Reg6[26:24] = 000 Reg6[26:24] = 001 Reg6[26:24] = 010 Reg6[26:24] = 011 Reg6[26:24] = 100 Reg6[26:24] = 101 Reg6[29:27] = 000 Reg6[29:27] = 001 Reg6[29:27] = 010 Reg6[29:27] = 011 Reg7[2:0] = 000 Reg7[2:0] = 001 Reg7[2:0] = 010 Reg7[2:0] = 011 Reg7[2:0] = 101 Reg7[5:3] = 000 Reg7[5:3] = 001 Reg7[5:3] = 101 Reg7[8:6] = 000 Reg7[8:6] = 001 Reg7[11:9] = 000 Reg7[11:9] = 001 Reg7[11:9] = 010 Reg7[11:9] = 011 Reg7[11:9] = 110 Reg7[14:12] = 000 Reg7[14:12] = 001 Reg7[14:12] = 011 Reg7[14:12] = 100
PULLUP/ PULLDN PD100, PU20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD9
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G1
LZ
DVDD9
PU100, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 2 mA (Lv) 6 mA (Hv)
A, F, G1 A, F, G1
LZ LZ
DVDD9 DVDD9
PU20, PD20
2 mA (Lv) 6 mA (Hv)
A, F
LZ
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
63
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. T19 SIGNAL NAME MPUIO4 EXT_DMA_REQ1 LED2 UWIRE.CS2 SPIF.CS2 MCBSP3.DR N15 MPUIO2 EXT_DMA_REQ0 UWIRE.CS1 SPIF.CS1 U20 U19 MPU_RST MPUIO14 MPUIO1 RTCK SPIF.SCK T18 V20 U18 I2C.SCL I2C.SDA GPIO48 UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR SPIF.DIN GPIO47
TYPE I/O I O O O I I/O I O O I I/O I/O I/O I/O I/O/Z I/O/Z I I O I I I/O I/O
MUX CTRL SETTING Reg7[17:15] = 000 Reg7[17:15] = 001 Reg7[17:15] = 010 Reg7[17:15] = 011 Reg7[17:15] = 100 Reg7[17:15] = 110 Reg7[20:18] = 000 Reg7[20:18] = 001 Reg7[20:18] = 010 Reg7[20:18] = 110 Reg9[8:6] = 000 Reg9[8:6] = 110 Reg7[23:21] = 000 Reg7[23:21] = 001 Reg7[23:21] = 110 Reg7[26:24] = 000 Reg7[29:27] = 000 Reg7[29:27] = 111 Reg8[2:0] = 000 Reg8[2:0] = 001 Reg8[2:0] = 010 Reg8[2:0] = 011 Reg8[2:0] = 110 Reg8[2:0] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# LZ
SUPPLY DVDD9
PU100, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD9
2 mA (Lv) 6 mA (Hv) PU100, PD20 4 mA (Lv) 8 mA (Hv)
A, F A, F
- Z
DVDD9 DVDD9
PRODUCT PREVIEW
2 mA (Lv) 6 mA (Hv) 2 mA (Lv) 6 mA (Hv) PU20, PD20 4 mA (Lv) 8 mA (Hv)
D D A, F
Z Z LZ
DVDD9 DVDD9 DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
64
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. W21 SIGNAL NAME UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UART3.RTS MCBSP3.DXZ SPIF.DOUT GPIO46 V19 UWIRE.SCLK KB.C[7] MPUIO1 UART3.CTS N14 Z_STATE UWIRE.CS0 MCBSP3.CLKX UART3.TX SPIF.CS0 GPIO45 P15 Z_STATE UWIRE.CS3 KB.C[6] SPIF.CS3 UART3.RX Z_STATE GPIO44 W19 BFAIL/EXT_FIQ UART3.CTS UART1.DSR MMC2.DATDIR1 AA20
TYPE O O O O O O/Z I/O I/O O O I/O I Z O I/O O I/O I/O Z O O O I Z I/O I I I O O I/O
MUX CTRL SETTING Reg8[5:3] = 000 Reg8[5:3] = 001 Reg8[5:3] = 010 Reg8[5:3] = 011 Reg8[5:3] = 100 Reg8[5:3] = 101 Reg8[5:3] = 110 Reg8[5:3] = 111 Reg8[8:6] = 000 Reg8[8:6] = 001 Reg8[8:6] = 010 Reg8[8:6] = 100 Reg8[11:9] = 001 Reg8[11:9] = 010 Reg8[11:9] = 100 Reg8[11:9] = 110 Reg8[11:9] = 111 Reg8[14:12] = 000 Reg8[14:12] = 001 Reg8[14:12] = 010 Reg8[14:12] = 011 Reg8[14:12] = 100 Reg8[14:12] = 110 Reg8[14:12] = 111 Reg8[17:15] = 000 Reg8[17:15] = 001 Reg8[17:15] = 010 Reg8[17:15] = 110 Reg9[11:9] = 000 Reg9[11:9] = 111 Reg8[11:9] = 000
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# 0
SUPPLY DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
Z
DVDD9
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
Z
DVDD9
RST_OUT GPIO41
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
0
DVDD9
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
65
PRODUCT PREVIEW
PU100, PD20
4 mA (Lv) 8 mA (Hv)
A, F
Z
DVDD9
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. V18 Y19 AA19 SIGNAL NAME CONF TDI TDO VLYNQ.TX0 V17 W18 Y18 V16 TMS TCK TRST EMU0 EMU1 RTCK MCSI1.SYNC MCBSP3.DR USB1.VP MCBSP3.FSX P14 MCSI1.CLK MCBSP3.DX USB1.VM TDI MCBSP3.CLKX GPIO43 W16 Z_STATE MCBSP3.CLKX USB1.TXEN MCSI1.DIN Z_STATE GPIO42
TYPE I I O TBD I I I I/O I/O I/O I/O I I I/O I/O O I I I/O I/O Z I/O O I Z I/O
MUX CTRL SETTING NA NA NA TBD NA NA NA NA NA NA RegA[5:3] = 000 RegA[5:3] = 001 RegA[5:3] = 010 RegA[5:3] = 100 RegA[8:6] = 000 RegA[5:3] = 001 RegA[5:3] = 010 RegA[5:3] = 011 RegA[5:3] = 100 RegA[5:3] = 111 Reg9[5:3] = 000 Reg9[5:3] = 001 Reg9[5:3] = 010 Reg9[5:3] = 100 Reg9[5:3] = 110 Reg9[5:3] = 111
PULLUP/ PULLDN PU20, PD20 PD100, PU20
BUFFER STRENGTH
OTHER A A
RESET STATE# LZ LZ -
SUPPLY DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD7
4 mA (Lv) 8 mA (Hv) PD100, PU20 PD100, PU20 PU20, PD20 PU100, PD20 PU100, PD20 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 11 mA (Hv) PU20, PD20 4 mA (Lv) 8 mA (Hv) A A A A A A A, F, G1
LZ LZ - Input Input - LZ
PRODUCT PREVIEW
W17 Y17 AA17
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD7
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
66
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. V15 SIGNAL NAME MCSI1.DIN USB1.RCV EMU1 MCBSP3.DR SSI.ACWAKE GPIO56 W15 BCLKREQ UART3.CTS MMC2.DAT2 GPIO40 Y15 BCLK UART3.RTS CAM.OUTCLK GPIO17 AA15 LOW_STATE UART1.RTS UART1.IRSHDN Z_STATE GPIO39 R14 UART1.CTS UART1.IRSEL GPIO38 V14 UART1.RX UART1.IRRX GPIO37 Y14 LOW_STATE UART1.TX UART1.IRTX CCP.DATAM
TYPE I I I/O I O I/O I I I/O I/O O O O I/O O O O Z I/O I O I/O I I I/O O O O I
MUX CTRL SETTING RegA[11:9] = 000 RegA[11:9] = 001 RegA[11:9] = 011 RegA[11:9] = 100 RegA[11:9] = 110 RegA[11:9] = 111 Reg9[29:27] = 000 Reg9[29:27] = 001 Reg9[29:27] = 110 Reg9[29:27] = 111 RegA[2:0] = 000 RegA[2:0] = 001 RegA[2:0] = 110 RegA[2:0] = 111 Reg9[14:12] = 000 Reg9[14:12] = 001 Reg9[14:12] = 010 Reg9[14:12] = 110 Reg9[14:12] = 111 Reg9[17:15] = 000 Reg9[17:15] = 010 Reg9[17:15] = 111 Reg9[20:18] = 000 Reg9[20:18] = 010 Reg9[20:18] = 111 Reg9[23:21] = 000 Reg9[23:21] = 001 Reg9[23:21] = 010 Reg9[23:21] = 110
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD7
2 mA (Lv) 6 mA (Hv)
A, B, F, G1
0
DVDD7
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
67
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. W14 SIGNAL NAME MCSI1.DOUT USB1.TXD TDO MCBSP3.DX CCP.DATAP GPIO18 R13 CLK32K_OUT MPUIO0 USB1.SPEED UART1.TX GPIO36 V13 OSC32K_IN OSC32K_OUT RTC_WAKE_INT USB1.SE0 RST_HOST_OUT CCP.CLKM GPIO55 Y12 P13 R12 W11 RTC_ON_NOFF CCP.CLKP CLK32K_IN PWRON_RESET MMC.DAT3 MPUIO9 MPUIO6 CFLASH.CD1 SSI.ACFLAG V11 MMC.CLK SSI.CARDY GPIO57
TYPE O O O O I I/O O I/O O O I/O - - O O O I I/O I I I I I/O I/O I/O I O O I I/O
MUX CTRL SETTING Reg9[26:24] = 000 Reg9[26:24] = 001 Reg9[26:24] = 011 Reg9[26:24] = 100 Reg9[26:24] = 110 Reg9[26:24] = 111 RegA[14:12] = 000 RegA[14:12] = 100 RegA[14:12] = 101 RegA[14:12] = 110 RegA[14:12] = 111 NA NA Reg9[2:0] = 000 Reg9[2:0] = 100 Reg9[2:0] = 101 Reg9[2:0] = 110 Reg9[2:0] = 111 Reg8[20:18] = 000 Reg8[20:18] = 110 RegA[17:15] = 000 NA Reg10[17:15] = 000 Reg10[17:15] = 001 Reg10[17:15] = 010 Reg10[17:15] = 011 Reg10[17:15] = 110 RegA[23:21] = 000 RegA[23:21] = 101 RegA[23:21] = 110
PULLUP/ PULLDN
BUFFER STRENGTH 2 mA (Lv) 6 mA (Hv)
OTHER A, B, F, G1, H3
RESET STATE# 0
SUPPLY DVDD7
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A
U
DVDDRTC
E E 2 mA (Lv) 6 mA (Hv) A, B
NA NA 0
NA NA DVDDRTC
PRODUCT PREVIEW
AA13 W13
2 mA (Lv) 6 mA (Hv)
A, B, G1 A A
Z Input Input Z
DVDDRTC DVDDRTC DVDDRTC DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
0
DVDD6
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
68
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. R11 SIGNAL NAME MMC.DAT0/SPI.DI Z_STATE CFLASH.IOIS16 SSI.ACRDY GPIO58 W10 MMC.DAT2 Z_STATE MPUIO11 CFLASH.RFSFT SSI.CAFLAG V10 MMC.DAT1 MPUIO10 MPUIO7 CFLASH.IRFQ SSI.ACDATA P11 MMC.CMD/SPI.DO CFLASH.CD2 SSI.CADATA GPIO55 Y10 MCSI2.CLK USB2.SUSP USB0.SUSP MMC2.CLK GPIO27 AA9 MCSI2.DIN USB2.VP USB0.VP GPIO26
TYPE I/O Z I O I/O I/O Z I/O O I I/O I/O I/O I O I/O I I I/O I/O O O O I/O I I I I/O
MUX CTRL SETTING RegB[2:0] = 000 RegB[2:0] = 001 RegB[2:0] = 011 RegB[2:0] = 110 RegB[2:0] = 111 RegA[20:18] = 000 RegA[20:18] = 001 RegA[20:18] = 010 RegA[20:18] = 011 RegA[20:18] = 110 RegA[26:24] = 000 RegA[26:24] = 001 RegA[26:24] = 010 RegA[26:24] = 011 RegA[26:24] = 110 RegA[29:27] = 000 RegA[29:27] = 011 RegA[29:27] = 110 RegA[29:27] = 111 RegB[5:3] = 000 RegB[5:3] = 001 RegB[5:3] = 101 RegB[5:3] = 110 RegB[5:3] = 111 RegB[8:6] = 000 RegB[8:6] = 001 RegB[8:6] = 101 RegB[8:6] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G1
RESET STATE# Z
SUPPLY DVDD6
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
PD100, PU20
4 mA (Lv) 8 mA (Hv)
A, F, G1
Z
DVDD6
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 - Revised March 2004
SPRS231B
69
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. W9 SIGNAL NAME MCSI2.DOUT USB2.TXEN USB0.TXEN Z_STATE GPIO25 V9 MCSI2.SYNC GPIO7 USB2.SPEED USB0.SPEED MMC2.CMDDIR R10 MCLKREQ EXT_MASTER_REQ UART2.RX MMC2.DAT3 GPIO23 W8 GPIO9 EMU0 MCSI1.SYNC MMC2.DAT0/SPI.DI Y8 GPIO8 TRST MCSI1.DOUT MMC2.CMD/SPI.DO V8 MPUIO3 MMC2.DAT1 P10 MCBSP2.DR MCBSP2.DX MCBSP2.DXZ GPIO22 W7 MCBSP2.FSX VLYNQ.RX1 GPIO21
TYPE O O O Z I/O I/O I/O O O O I O I I/O I/O I/O I/O I/O I/O I/O I O I/O I/O I/O I O O/Z I/O I/O I I/O
MUX CTRL SETTING RegB[11:9] = 000 RegB[11:9] = 001 RegB[11:9] = 101 RegB[11:9] = 110 RegB[11:9] = 111 RegB[14:12] = 000 RegB[14:12] = 001 RegB[14:12] = 010 RegB[14:12] = 110 RegB[14:12] = 111 RegB[20:18] = 000 RegB[20:18] = 001 RegB[20:18] = 010 RegB[20:18] = 110 RegB[20:18] = 111 RegB[23:21] = 000 RegB[23:21] = 011 RegB[23:21] = 100 RegB[23:21] = 110 RegB[26:24] = 000 RegB[26:24] = 011 RegB[26:24] = 100 RegB[26:24] = 110 RegB[29:27] = 000 RegB[29:27] = 110 RegC[2:0] = 000 RegC[2:0] = 001 RegC[2:0] = 010 RegC[2:0] = 111 RegC[5:3] = 000 RegC[5:3] = 011 RegC[5:3] = 111
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G2
RESET STATE# 0
SUPPLY DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PRODUCT PREVIEW
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G3
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G3
LZ
DVDD3
PU20, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F, G1
LZ
DVDD3 DVDD3
A, F, G2
LZ
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
LZ
DVDD3
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
70
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. V7 SIGNAL NAME MCBSP2.CLKR GPIO11 VLYNQ.CLK Y6 MCBSP2.CLKX VLYNQ.TX1 GPIO20 W6 MCBSP2.FSR GPIO12 VLYNQ.RX0 AA5 MCBSP2.DX MCBSP2.DR MCBSP2.DXZ VLYNQ.TX0 GPIO19 R9 UART2.RX USB2.VM USB0.VM GPIO18 Y5 UART2.CTS USB2.RCV GPIO7 USB0.RCV W5 LOW_STATE UART2.RTS USB2.SE0 MPUIO5 MPUIO12 USB0.SE0 LOW_STATE
TYPE I/O I/O I/O I/O O I/O I/O I/O I O I O/Z O I/O I I I I/O I I I/O I O O O I/O I/O O O
MUX CTRL SETTING RegC[8:6] = 000 RegC[8:6] = 001 RegC[8:6] = 011 RegC[11:9] = 000 RegC[11:9] = 011 RegC[11:9] = 111 RegC[14:12] = 000 RegC[14:12] = 001 RegC[14:12] = 011 RegC[17:15] = 000 RegC[17:15] = 001 RegC[17:15] = 010 RegC[17:15] = 111 RegC[20:18] = 000 RegC[20:18] = 001 RegC[20:18] = 101 RegC[20:18] = 111 RegC[23:21] = 000 RegC[23:21] = 001 RegC[23:21] = 010 RegC[23:21] = 101 RegC[26:24] = 000 RegC[26:24] = 001 RegC[26:24] = 010 RegC[26:24] = 011 RegC[26:24] = 100 RegC[26:24] = 101 RegC[26:24] = 110 RegC[17:15] = 011
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 11 mA (Hv)
OTHER A, F
RESET STATE# Z
SUPPLY DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
LZ
DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F
Z
DVDD3
PU20, PD20
4 mA (Lv) 11 mA (Hv)
A, F, G2
0
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F
LZ
DVDD3
4 mA (Lv) 8 mA (Hv)
A, F, G2
0
DVDD3
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
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71
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. V6 SIGNAL NAME LOW_STATE UART2.TX USB2.TXD USB0.TXD Z_STATE GPIO17 Y4 V5 UART2.BCLK SYS_CLK_IN MCLK MMC2.DATDIR0 GPIO24 W4 USB.PUEN USB.CLKO USB.PUDIS Z_STATE LOW_POWER GPIO58 P9 USB.DP I2C.SDA UART1.RX USB.PUEN R8 USB.DM I2C.SCL UART1.TX Z_STATE Y2 W3 Y1 V4 W2

TYPE O O O O Z I/O O I O O I/O O O O Z O I/O I/O I/O/Z I O I/O I/O/Z O Z I O O I/O O O
MUX CTRL SETTING RegC[29:27] = 000 RegC[29:27] = 001 RegC[29:27] = 010 RegC[29:27] = 101 RegC[29:27] = 110 RegC[29:27] = 111 RegD[2:0] = 000 RegD[2:0] = 110 RegB[17:15] = 000 RegB[17:15] = 110 RegB[17:15] = 111 RegD[5:3] = 000 RegD[5:3] = 001 RegD[5:3] = 011 RegD[5:3] = 100 RegD[5:3] = 110 RegD[5:3] = 111 USBTCTL[6:4] = 000 USBTCTL[6:4] = 100 USBTCTL[6:4] = 101 USBTCTL[6:4] = 111 USBTCTL[6:4] = 100 USBTCTL[6:4] = 101 USBTCTL[6:4] = 111 NA NA RegA[2:0] = 000 RegA[2:0] = 111 NA NA
PULLUP/ PULLDN PU20, PD20
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F, G2
RESET STATE# 0
SUPPLY DVDD3
4 mA (Lv) 8 mA (Hv) PU20, PD20 4 mA (Lv) 8 mA (Hv)
A, F, G2 A, F, G1
0 0
DVDD3 DVDD3
PU20, PD20
4 mA (Lv) 8 mA (Hv)
A, F, G1
1
DVDD2
PRODUCT PREVIEW
18.3 mA (in USB mode)
C
Z
DVDD2
18.3 mA (in USB mode)
C
Z
DVDD2
OSC1_IN OSC1_OUT FLASH.CS1U GPIO16 FLASH.WP FLASH.WE
E E 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) A, F A A
NA NA 1 0 1
NA NA DVDD5 DVDD5 DVDD5
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
72
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Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. W1 U4 E1 L7 K3 K4 L8 F2 J3 F4 J2 K7 H3 H4 K8 G2 G3 G4 F3 J7 E3 F4 D2

SIGNAL NAME FLASH.RP FLASH.CS2UWE FLASH.OE FLASH.A[25:17]
TYPE O O O O
MUX CTRL SETTING RegF[23:21] = 000 RegF[23:21] = 001 NA NA
PULLUP/ PULLDN
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
OTHER A A A, G1
RESET STATE# 0 1 0
SUPPLY DVDD5 DVDD5 DVDD5
FLASH.A[16] FLASH.A[15] FLASH.A[14] FLASH.A[13] FLASH.A[12] FLASH.A[11] FLASH.A[10] FLASH.A[9] FLASH.A[8] FLASH.A[7] FLASH.A[6] FLASH.A[5]
O O O O O O O O O O O O
Reg11[5:3] = 000 Reg11[8:6] = 000 Reg11[11:9] = 000 Reg11[14:12] = 000 Reg11[17:15] = 000 Reg11[20:18] = 000 Reg11[23:21] = 000 Reg11[26:24] = 000 Reg12[5:3] = 000 Reg12[8:6] = 000 Reg12[11:9] = 000 Reg12[14:12] = 000
PU20, PD20
4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1 A, G1
0 0 0 1 0 0 0 0 0 0 0 0
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv)
PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
PU20, PD20 PU20, PD20 PU20, PD20
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
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73
PRODUCT PREVIEW
Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. E4 C1 D3 J8 V3 T4 U3 U1 P8 T3 T2 R4 R3 R2 P7 P4 P2 N7 N2 N4 N3 SIGNAL NAME FLASH.A[4] FLASH.A[3] FLASH.A[2] FLASH.A[1] FLASH.D[15:0] TYPE O O O O I/O MUX CTRL SETTING Reg12[17:15] = 000 Reg12[20:18] = 000 Reg12[23:21] = 000 Reg12[26:24] = 000 NA PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20 BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 3 mA (Lv) 8 mA (Hv) 3 mA (Lv) 6 mA (Hv) OTHER A, G1 A, G1 A, G1 A, G1 A, K RESET STATE# 0 0 0 0 0 SUPPLY DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PRODUCT PREVIEW
FLASH.CLK FLASH.CS2UOE
O O I I/O O O O O I/O O O O O I/O O O I/O
Reg10[23:21] = 000 Reg10[23:21] = 001 RegF[29:27] = 000 RegF[29:27] = 001 NA RegD[8:6] = 000 RegD[8:6] = 000 RegD[8:6] = 000 Reg10[2:0] = 000 Reg10[2:0] = 001 Reg10[29:27] = 000 Reg10[29:27] = 001 Reg10[20:18] = 000 Reg10[20:18] = 001 Reg10[8:6] = 000 Reg10[8:6] = 001 Reg10[8:6] = 111 PU100, PD20
3 mA (Lv) 6 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, K, G1
0
DVDD5 DVDD5 DVDD5 DVDD5
V2
FLASH.RDY GPIO10
A, F
Input
L4 M4
FLASH.ADV FLASH.CS2 FLASH.BAA FLASH.CS2L
A A
1 1
M7
GPIO62 FLASH.CS0
4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv) 4 mA (Lv) 8 mA (Hv)
A, F, G1
Input
DVDD5 DVDD5 DVDD5 DVDD5
M3
FLASH.CS1 FLASH.CS1L
A
1
P3
FLASH.CS2U GPIO5
A, F
1
L3
FLASH.BE[0] FLASH.CS2UOE GPIO59
A, F
0
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
74
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Introduction
Table 2-4. ZZG Package Terminal Characteristics (Continued)
ZZG BALL NO. M8 SIGNAL NAME FLASH.BE[1] FLASH.CS2UWE GPIO60 N8
TYPE O O I/O O I/O
MUX CTRL SETTING Reg10[5:3] = 000 Reg10[5:3] = 001 Reg10[5:3] = 111 Reg10[26:24] = 000 Reg10[26:24] = 111
PULLUP/ PULLDN
BUFFER STRENGTH 4 mA (Lv) 8 mA (Hv)
OTHER A, F
RESET STATE# 0
SUPPLY DVDD5
FLASH.CS3 GPIO3
4 mA (Lv) 8 mA (Hv)
A, F
1
DVDD5
NOTES: 3. NA denotes no multiplexing on the ball 4. `Regx' denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
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75
PRODUCT PREVIEW
I = Input, O = Output, Z = High-Impedance PD20 = 20-A internal pulldown, PD100=100-A internal pulldown, PU20 = 20-A internal pullup, PU100 = 100-A internal pullup Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V) A = Standard LVCMOS input/output G1 = Terminal may be gated by BFAIL B = SUBLVDS input/ouput G2 = Terminal may be gated by GPIO9 and MPUIO3 C = USB transceiver input/ouput G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset D = I2C input/output buffers H1 = Terminal may be 3-stated by BFAIL input E = Analog oscillator terminals H3 = MCSI1.DOUT pin can be forced into a high-impedance F = Boundary-scannable terminal state by the OMAP5912 HIGH_IMP3 control bit K = Output buffer includes a serial resistor of 20 to match with PCB line impedance and ensure proper signal integrity # Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
Introduction
2.4
Signal Description
Table 2-5 provides a description of the signals on OMAP5912. Many signals are available on multiple pins, depending upon the software configuration of the pin multiplexing options. Table 2-5. Signal Description
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
EXTERNAL MEMORY INTERFACE FAST (EMIFF) SDRAM INTERFACE SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.DQML E7 A12 A2 D5 C7 G8 C14 D4 B4 C8 SDRAM chip-select DDR DQ strobe high DDR DQ strobe low SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes, and the REFR and MRS commands to SDRAM memory. SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memory. SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and 8-bit-wide accesses to SDRAM memory. SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB, REFR, and MRS commands to SDRAM memory. SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS commands to SDRAM memory. SDRAM address bus. Provides row and column address information to the SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a control signal to define specific commands to SDRAM memory. O I/O I/O O O
PRODUCT PREVIEW
SDRAM.DQMU
A8
D10
O
SDRAM.RAS SDRAM.WE SDRAM.A[13:0]
D4 E6 D10 E8 E9 F8 F9 C6 A10 E10 C8 D9 C3 F7 A1 B2 C4 C5 B10 C10 B11 B9 A11 B8 B12 C9 B7 A3 B6 B3 A5 A4 B5 B4 A7 A6 B13
H7 H8 H11 H9 H10 B8 B12 G9 G11 G12 B9 G10 A1 B6 B2 A2 C3 B3 C12 D12 D13 C11 C13 D11 D14 C10 D8 C4 C7 D5 D7 C5 C6 D6 C9 D9 H12
O O O
SDRAM.BA[1:0] SDRAM.D[15:0]
SDRAM bank address bus. Provides the bank address to SDRAM memories SDRAM data bus. SDRAM.D[15:0] provides data exchange between the traffic controller and SDRAM memory.
O I/O
SDRAM.CLK SDRAM.CLKX SDRAM.CKE
SDRAM clock. Clock for synchronization SDRAM memory commands/accesses. DDR clock. Inverted clock for synchronization DDR memory commands/accesses SDRAM clock enable (active-high). Asserting this signal enables the SDRAM clock for normal operation; negating puts SDRAM memory into low-power mode.
O O O
I = Input, O = Output, Z = High-Impedance
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
EXTERNAL MEMORY INTERFACE SLOW (EMIFS) FLASH AND ASYNCHRONOUS MEMORY INTERFACE FLASH.A[25:1] F3 J4 J2 H2 H5 F4 H4 H3 G6 G5 G2 G4 G3 F5 F1 F2 E1 D1 E2 C1 D2 E3 E4 C2 D3 N4 R1 P1 K7 M3 M4 N2 L5 N1 K6 L4 M2 J7 L2 M1 L1 K1 L6 E1 L7 K3 K4 L8 F2 J3 J4 J2 K7 H3 H4 K8 G2 G3 G4 F3 J7 E3 F4 D2 E4 C1 D3 J8 V3 T4 U3 U1 P8 T3 T2 R4 R3 R2 P7 P4 P2 N7 N2 N4 N3 V2 EMIFS address bus. Address output bus for all EMIFS accesses. O
FLASH.D[15:0]
FLASH.CLK FLASH.RDY
Flash clock. Clock output that is active during synchronous modes of flash operation for synchronous burst flash memories. Flash ready. Active-high ready input used to suspend the flash interface when the external memory or asynchronous device is not ready to continue the current cycle. Flash address valid. Active-low control signal used to indicate a valid address is present on the FLASH.A[25:1] bus. Flash burst advance acknowledge. Active-low control signal used with Advanced Micro Devices E burst flash. Flash byte enables. Active-low byte enable signals used to perform byte-wide accesses to memories or devices that support byte enables. Flash chip-select bit 0 Flash chip-select bit 1 Lower half of FLASH.CS1 address range Upper half of FLASH.CS1 address range Flash chip-select bit 2 Lower half of FLASH.CS2 address range Upper half of FLASH.CS2 address range
O I
FLASH.ADV FLASH.BAA FLASH.BE[1:0] FLASH.CS0 FLASH.CS1 FLASH.CS1L FLASH.CS1U FLASH.CS2 FLASH.CS2L FLASH.CS2U
H6 J8 K2 J1 J5 J3 J3 T1 J8 J8 K3
L4 M4 M8 L3 M7 M3 M3 Y1 M4 M4 P3
O O O O O O O O O O
I = Input, O = Output, Z = High-Impedance
Advanced Micro Devices is a trademark of Advanced Micro Devices, Inc. 77
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SPRS231B
PRODUCT PREVIEW
EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data during EMIFS accesses. The 16-bit data bus becomes address/data in case the EMIFS is configured in address/data multiplexed mode.
I/O
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
EXTERNAL MEMORY INTERFACE SLOW (EMIFS) FLASH AND ASYNCHRONOUS MEMORY INTERFACE (CONTINUED) FLASH.CS2UOE FLASH.CS2UWE FLASH.CS3 FLASH.OE FLASH.RP FLASH.WE FLASH.WP J1 K1 K2 N3 J6 M5 N3 P3 R3 L3 N3 M8 W1 N8 U4 W1 W2 V4 FLASH.CS2U gated with FLASH.OE. Output enable if EMIFS is used to interface with external flash. FLASH.CS2U gated with FLASH.WE. Write enable if EMIFS is used to interface with external flash. Flash chip-select bit 3. If MPU_BOOT is high and the device is an emulation device, select external boot memory. Flash output enable. Active-low output enable output for Flash or SRAM memories or asynchronous devices. Flash power down (TI Flash devices) or reset output (Intel Flash devices) Flash write enable. Active-low write enable output for Flash or SRAM memories or asynchronous devices. Flash write protect. Active-low output for hardware write protection feature on standard memory devices. CompactFlash INTERFACE CFLASH.IREQ CFLASH.CD1 CFLASH.CD2 CFLASH.IOIS16 CFLASH.RESET
O O O O O O O
PRODUCT PREVIEW
U9 P9 N7 R8 T9
V10 W11 P11 R11 W10
CompactFlash interrupt request Card detect Card detect 8/16 bits selection Reset
I I I I O
I = Input, O = Output, Z = High-Impedance
Intel is a registered trademark of Intel Corporation. 78
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
MULTIMEDIA CARD/SECURE DIGITAL INPUT/OUTPUT INTERFACES (MMC/SDIOs) MMC.CLK MMC.CMD/SPI.DO M8 N7 V11 P11 MMC/SDIO1 clock. Clock output to the MMC/SD card. MMC/SDIO1 command/SPI data output. MMC/SD commands are transferred to/from this pin. The pin functions as the data output during SPI mode. MMC/SDIO1 data bit 0/SPI input. MMC.DAT0/SPI.DI functions as data bit 0 during MMC and secure digital operation. The pin functions as the data input in generic SPI mode. SD card data bit 1. Data bit 1 is used in 4-bit secure digital mode. SD card data bit 2. Data bit 2 is used in 4-bit secure digital mode. SD card data bit 3. Data bit 3 is used in 4-bit secure digital mode. SPI clock. SPI clock output used during generic SPI mode operation. SPI ready. SPI ready input from SPI device used only in generic SPI mode operation. SPI chip-selects. SPI chip-selects used during generic SPI mode operation. O I/O
MMC.DAT0/SPI.DI
R8
R11
I/O
MMC.DAT1 MMC.DAT2 MMC.DAT3 SPI.CLK SPI.RDY SPI.CS1 SPI.CS2 SPI.CS3 MMC2.CLK MMC2.CLKIN MMC2.CMD/SPI.DO
U9 T9 L15 P9 M16 N17 L14 M17 L13 K12 P8 N17 P7 H15
V10 W10 M15 W11 M14 R18 P19 P20 P18 M19 Y10 R18 Y8 J19 V9 L15 W8 L18 V8 J18 W15 L19 R10 V5 W19
I/O I/O I/O O I O
MMC/SDIO2 clock. Clock output to the MMC/SD card. MMC/SDIO2 clock feedback MMC/SDIO2 command/SPI data output. MMC/SD commands are transferred to/from this pin. The pin functions as the data output during SPI mode. MMC/SDIO2 command direction control MMC/SDIO2 data bit 0/SPI serial Input. MMC2.DAT0/SPI.DI functions as data bit 0 during MMC and secure digital operation. The pin functions as the data input in generic SPI mode. MMC/SDIO2 card data bit 1 MMC/SDIO2 card data bit 2 MMC/SDIO2 card data bit 3 MMC/SDIO2 data bit 0 direction control MMC/SDIO2 data bit 1, 2, 3 direction control
O I I/O
MMC2.CMDDIR MMC2.DAT0/SPI.DI
U8 J12 U7
O I/O
MMC2.DAT1 MMC2.DAT2 MMC2.DAT3 MMC2.DATDIR0 MMC2.DATDIR1
J13 R6 H16 R12 J17 T7 U3 T17
I/O I/O I/O O O
I = Input, O = Output, Z = High-Impedance
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79
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
MULTICHANNEL BUFFERED SERIAL PORTS (McBSPs) MCBSP1.CLKX MCBSP1.CLKS MCBSP1.DR MCBSP1.DX MCBSP1.DXZ MCBSP1.FSX MCBSP2.CLKR MCBSP2.CLKX MCBSP2.DR F16 G13 G17 G14 G15 G15 G14 G15 G14 U6 U5 L8 T5 MCBSP2.DX MCBSP2.DXZ MCBSP2.FSR MCBSP2.FSX MCBSP3.CLKX L8 T5 L8 T5 R5 N6 U14 R17 U15 MCBSP3.DR N10 P14 P12 M14 MCBSP3.DX U15 R15 P11 MCBSP3.DXZ MCBSP3.FSX R15 L16 L13 L14 M17 N10
G21 G20 H20 H18 H15 H15 H18 H15 H18 V7 Y6 P10 AA5 P10 AA5 P10 AA5 W6 W7 W16 N14 P14 AA17 U18 V15 T19 P14 W21 W14 W21 N18 P18 P19 P20 AA17
McBSP1 bit clock McBSP1 clock input McBSP1 data input McBSP1 data output McBSP1 data output (for multichannel mode) McBSP1 frame synchronization McBSP2 receive clock McBSP2 transmit clock McBSP2 data input McBSP2 data output McBSP2 data output (for multichannel mode) McBSP2 receive frame synchronization McBSP2 transmit frame synchronization McBSP3 clock
I/O I I O O/Z I/O I/O I/O I O O/Z I/O I/O I/O
PRODUCT PREVIEW
McBSP3 data input
I
McBSP3 data output
O
McBSP3 data output (for multichannel mode) McBSP3 frame synchronization
O/Z I/O
I = Input, O = Output, Z = High-Impedance
80
SPRS231B
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
MULTICHANNEL SERIAL INTERFACES (MCSIs) MCSI1.CLK MCSI1.DIN U15 L15 L14 P12 U14 MCSI1.DOUT MCSI1.SYNC MCSI2.CLK MCSI2.DIN MCSI2.DOUT MCSI2.SYNC SPIF.CS0 SPIF.CS1 SPIF.CS2 SPIF.CS3 SPIF.SCK SPIF.DIN SPIF.DOUT P11 P7 N10 U7 P8 R7 T8 U8 R17 L12 M14 R16 N15 M17 P14 N17 R15 SSI.ACDATA SSI.ACFLAG SSI.ACRDY SSI.ACWAKE SSI.CADATA SSI.CAFLAG SSI.CARDY
P14 M15 P19 V15 W16 W14 Y8 AA17 W8 Y10 AA9 W9 V9 N14 N15 T19 P15 U19 P20 U18 R18 W21
MCSI1 bit clock MCSI1 data input
I/O I
MCSI1 data output MCSI1 frame synchronization MCSI2 bit clock MCSI2 data input MCSI2 data output MCSI2 frame synchronization SERIAL PORT INTERFACE (SPI) SPI output chip-selects in master mode/input chip-select when SPI is in slave mode.
O I/O I/O I O I/O I/O O
SPI output clock in master mode. SPI input clock in slave mode. SPI data-In in master mode. SPI data-out in slave mode. SPI data-out in master mode. SPI data-in in slave mode.
I/O I/O I/O I/O I/O
SYNCHRONOUS SERIAL INTERCONNECT (SSI) U9 P9 R8 P12 N7 T9 M8 V10 W11 R11 V15 P11 W10 V11 Data transmit (SST) Flag associated with transmitting data (SST) CMT ready signal (SST) CMT wake up Data receive (SSR) Flag associated with receiving data (SSR) APE ready signal (SSR) O O O O I I I
I = Input, O = Output, Z = High-Impedance
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SPRS231B
81
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) INTERFACES UART1.CTS UART1.DSR UART1.DTR UART1.RTS UART1.RX UART1.TX M9 P14 T17 R15 N16 R11 U13 T2 T12 U1 U12 UART1.IRTX T12 U13 M9 R11 P5 P6 J12 UART2.RTS UART2.RX T4 K12 U4 T7 K15 UART2.TX UART3.CTS R4 K17 R12 T17 J14 P15 UART3.DSR UART3.DTR UART3.RTS P14 R15 M15 L10 J16 N16 R15
R14 U18 W19 W21 T20 AA15 V14 P9 Y14 R8 R13 Y14 V14 R14 AA15 Y4 Y5 L15 W5 M19 R9 R10 L14 V6 M18 W15 W19 K15 V19 U18 W21 R19 Y15 K14 T20 W21
UART1 clear to send UART1 data set ready UART1 data terminal ready UART1 request to send UART1 receive data UART1 transmit data
I I O O I O
UART1 IrDA transmit data UART1 IrDA receive data UART1 IrDA mode select for external transceiver UART1 IrDA mode select for external transceiver UART2 baud clock. A clock of 16x UART2 clear to send UART2 request to send UART2 receive data
O I O O O I O I
PRODUCT PREVIEW
UART1.IRRX UART1.IRSEL UART1.IRSHDN UART2.BCLK UART2.CTS
UART2 transmit data UART3 clear to send
O I
UART3 data set ready UART3 data terminal ready UART3 request to send in UART mode SD_MODE in IrDA mode
I O O
I = Input, O = Output, Z = High-Impedance
82
SPRS231B
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) INTERFACES (CONTINUED) UART3.RX K15 H13 R16 UART3.TX K17 J11 R17 USB.DM USB.DP USB0.RCV USB0.SE0 USB0.SPEED USB0.SUSP USB0.TXD USB0.TXEN USB0.VM USB0.VP USB1.RCV USB1.SE0 USB1.SPEED USB1.SUSP USB1.TXD USB1.TXEN USB1.VM USB1.VP USB2.RCV USB2.SE0 USB2.SPEED USB2.SUSP USB2.TXD USB2.TXEN USB2.VM USB2.VP
L14 K19 P15 M18 K18 N14
UART3 receive data
I
UART3 transmit data
O
USB (INTEGRATED TRANSCEIVER) U1 T2 P6 T4 U8 P8 R4 T8 U4 R7 P12 N9 U12 H14 P11 U14 U15 N10 P6 T4 U8 P8 R4 T8 U4 R7 R8 P9 Y5 W5 V9 Y10 V6 W9 R9 AA9 V15 W13 R13 J20 W14 W16 P14 AA17 Y5 W5 V9 Y10 V6 W9 R9 AA9 USB differential (-) line USB differential (+) line USB PORT 0 USB port 0 receive data USB port 0 single-ended zero USB 0 speed USB 0 suspend USB port 0 transmit data USB port 0 transmit enable USB port 0 V minus receive data USB port 0 V plus receive data USB PORT 1 USB port 1 receive data USB port 1 single-ended zero USB port 1 bus segment speed control USB port 1 bus segment suspend control USB port 1 transmit data USB port 1 transmit enable USB port 1 V minus receive data USB port 1 V plus receive data USB PORT 2 USB port 2 receive data USB port 2 single-ended zero Low-speed USB device or full-speed USB device USB port 2 bus segment suspend control USB port 2 transmit data USB port 2 transmit enable USB port 2 V minus receive data USB port 2 V plus receive data I O O O O O I I I O O O O O I I I O O O O I I O I/O I/O
I = Input, O = Output, Z = High-Impedance
December 2003 - Revised March 2004
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83
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
UNIVERSAL SERIAL BUS (USB) MISCELLANEOUS SIGNALS USB.CLKO USB.VBUS P4 N17 W4 R18 USB clock output. 6-MHz divided clock output of the internal USB DPLL provided for reference. Common for all USB host and function peripherals. USB voltage bus enable. USB.VBUS is an input which allows the OMAP5912 device to detect whether the USB cable is connected or not. USB.VBUS must be connected to USB power from the USB cable through a voltage translation buffer to convert the 5-V power from the USB cable to within the 3.3-V nominal range specified for the OMAP device input. USB pullup enable USB pullup disable (I2C) MASTER AND SLAVE INTERFACE I/O I/O I2C serial clock I2C serial data HDQ/1-Wire INTERFACE HDQ K13 N20 HDQ/1-Wire interface. HDQ optionally implements one of two serial protocols: HDQ or 1-Wire. MICROWIRE INTERFACE UWIRE.CS0 UWIRE.CS1 UWIRE.CS2 UWIRE.CS3 UWIRE.SCLK UWIRE.SDI UWIRE.SDO
O I
USB.PUEN USB.PUDIS I2C.SCL I2C.SDA
P4 T2 P4 P16 U1 M11 T2
W4 P9 W4 T18 R8 V20 P9
O O
INTER-INTEGRATED CIRCUIT
PRODUCT PREVIEW
I/O
R17 H16 L12 M14 R16 H15 P15 G16 P14 H17 R15 H12
N14 J18 N15 T19 P15 J19 V19 J15 U18 J14 W21 H19
MICROWIRE chip-select 0. The output selects a single MICROWIRE device (configurable as active-high or active-low). MICROWIRE chip-select 1 MICROWIRE chip-select 2 MICROWIRE chip-select 3 MICROWIRE serial clock. This pin drives a clock to a MICROWIRE device. The active edge is software-configurable. MICROWIRE serial data input MICROWIRE serial data output
O
O I O
I = Input, O = Output, Z = High-Impedance
MICROWIRE is a registered trademark of National Semiconductor Corporation. 84
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION CAMERA INTERFACE CAM.OUTCLK CAM.D[7:0] L10 H16 H15 H17 J11 H13 J14 J16 J17 J12 G16 K12 J13 N9 P10 T12 P11 H12 Y15 J18 J19 J14 K18 K19 K15 K14 L19 L15 J15 M19 L18 W13 Y12 Y14 W14 H19 Camera output clock Camera digital image data bits O I TYPE
CAM.HS CAM.LCLK CAM.RSTZ CAM.VS CCP.CLKM CCP.CLKP CCP.DATAM CCP.DATAP CAM.EXCLK
Camera interface horizontal synchronization. Horizontal synchronization input from external camera sensor. Camera interface line clock. Input clock to provide external timing reference from camera sensor logic Camera interface reset. Reset output used to reset or Initialize external camera sensor logic. Camera vertical synchronization COMPACT CAMERA PORT (CCP) INTERFACE Camera differential clock Camera differential data Camera differential data Camera interface external clock. Output clock used to provide a timing reference to a camera sensor. VLYNQ INTERFACE Camera differential clock. Clock up to 208 MHz.
I I O I I I I I O
VLYNQ.CLK
E16 U6 L17
H14 V7 N19 F19 W6 N18 G18 W7 N20 E20 AA15 N21 E19 Y6 M20
VLYNQ clock
I/O
VLYNQ.RX0
E17 R5 L16
VLYNQ receive data 0
I
VLYNQ.RX1
F15 N6 K13
VLYNQ receive data 1
I
VLYNQ.TX0
D17 R11 K14
VLYNQ transmit data 0
O
VLYNQ.TX1
F13 U5 K16
VLYNQ transmit data 1
O
I = Input, O = Output, Z = High-Impedance
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85
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION LCD AND LCDCONV INTERFACE LCD.AC F10 B15 LCD AC-bias. LCD.AC signals the LCD display to switch the polarity of the row and column power supplies to counteract charge buildup causing DC offset. In TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the pixel clock. Blue bit 0 in 18-bit LCD output mode LCD horizontal sync. LCD_HSYNC is the line clock that signals the end of a line of pixels to the LCD display panel. In TFT mode, LCD_HSYNC is the horizontal synchronization signal. LCD pixel clock output. Clock output provided to synchronize pixel data to LCD display panels. In passive mode, LCD_PCLK transitions only when LCD.P[15:0] is valid. In active mode, LCD_PCLK transitions continuously and LCD.AC is used as the output enable when LCD.P[15:0] is valid. LCD pixel data bits O TYPE
LCD.BLUE0 LCD.HS
L17 D15
N19 C20
O O
LCD.PCLK
A14
C15
O
LCD.P[15:0]
PRODUCT PREVIEW
C12 D12 E11 A13 B14 A15 F11 C13 D13 A16 C15 E12 D14 C16 B16 A17 K14 B15
D15 C16 A17 G13 B17 C17 D16 D17 C18 B19 A20 H13 G14 C19 B21 D18 N21 B18
O
LCD.RED0 LCD.VS
Red bit 0 in 18-bit LCD output mode LCD vertical synchronization (sync) output. LCD.VS is the frame clock that signals the start of a new frame of pixels to the LCD display panel. In TFT mode, LCD.VS is the vertical synchronization signal. SoSSI command/data control LCD chip-select SoSSI data bits
O O
SPECIALLY OPTIMIZED SCREEN INTERFACE (SoSSI) SOSSI.CMD SOSSI.CS SOSSI.D[15:0] F10 D15 C12 D12 E11 A13 B14 A15 F11 C13 D13 A16 C15 E12 D14 C16 B16 A17 B15 A14 G13 B15 C20 D15 C16 A17 G13 B17 C17 D16 D17 C18 B19 A20 H13 G14 C19 B21 D18 B18 C15 G20 O O I/O
SOSSI.RD SOSSI.WR SOSSI.TE
Read enable for SoSSI Write enable for SoSSI Tearing effect removal
O O I
I = Input, O = Output, Z = High-Impedance
86
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION JTAG/EMULATION INTERFACE TCK P13 L15 RTCK RTDX.D[0] RTDX.D[1] RTDX.D[2] RTDX.D[3] TDI TDO T14 N15 M16 L13 L15 K13 U17 U15 T15 P11 TMS TRST M10 L14 R13 P7 EMU1 N11 P12 EMU0 U16 U7
TYPE
W18 M15 Y17 U19 M14 P18 M15 N20 Y19 P14 AA19 W14 V17 P19 Y18 Y8 W17 V15 V16 W8
IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on the test access port (TAP) of input signals TDI and TMS are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal TDO occur on the falling edge of TCK. ARM926EJ-S return clock emulation Emulation data transmit Emulation data transmit Emulation data transmit Emulation data transmit IEEE Standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on the rising edge of TCK. IEEE Standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. IEEE Standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK. IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is not connected, or driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Emulation pin 1. When TRST is driven high, EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. EMU0 V16 Emulation pin 0. When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1449.1 scan system.
I
I/O I/O I/O I/O I/O I O
I I
I/O
I/O
I = Input, O = Output, Z = High-Impedance
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PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
SHARED GENERAL-PURPOSE IO MODULES (GPIOs) GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 GPIO55 E15 J5 G13 B17 K2 J1 R8 P4 M8 H12 P12 N7 N9 GPIO54 GPIO53 GPIO52 GPIO51 GPIO50 GPIO49 GPIO48
E18 M7 G20 D19 M8 L3 R11 W4 V11 H19 V15 P11 W13 G21 H15 H18 H20 M18 L14 V20
General-Purpose IOs module 4. Each GPIO pin can be used by either the DSP core or the MPU core. Control of each GPIO pin between the two cores is selected by the MPU via control registers. Each GPIO pin may also be configured to cause an interrupt to its respective core processor.
I/O
PRODUCT PREVIEW
F16 G15 G14 G17 K17 K15 M11
I = Input, O = Output, Z = High-Impedance
88
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
SHARED GENERAL-PURPOSE IO MODULES (GPIOs) (CONTINUED) GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32
P14 R15 R17 R16 U15 U14 N12 R12 R11 G16 M9 J12 U13 K12 U12 H16 D12 H15 E11 H17 A13 J11 B14
U18 W21 N14 P15 P14 W16 AA20 W15 AA15 J15 R14 L15 M19 R13 J18 C16 J19 A17 J14 G13 K18 B17 V14
General-Purpose IOs module 3. Each GPIO pin can be used by either the DSP core or the MPU core. Control of each GPIO pin between the two cores is selected by the MPU via control registers. Each GPIO pin may also be configured to cause an interrupt to its respective core processor.
I/O
I = Input, O = Output, Z = High-Impedance
December 2003 - Revised March 2004
SPRS231B
89
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
SHARED GENERAL-PURPOSE IO MODULES (GPIOs) (CONTINUED) GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
H13 A15 J14 F11 J16 C13 F17 P8 D16 R7 T8 U3 T7 L8 N6 U5 T5 P11 U4 L10 R4 T1
K19 C17 K15 D16 K14 D17 G19 Y10 C21 AA9 W9 V5 R10 P10 W7 Y6 AA5 W14 R9 Y15 V6 Y1
General-Purpose IOs module 2. Each GPIO pin can be used by either the DSP core or the MPU core. Control of each GPIO pin between the two cores is selected by the MPU via control registers. Each GPIO pin may also be configured to cause an interrupt to its respective core processor.
I/O
PRODUCT PREVIEW
I = Input, O = Output, Z = High-Impedance
90
SPRS231B
December 2003 - Revised March 2004
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION TYPE
SHARED GENERAL-PURPOSE IO MODULES (GPIOs) (CONTINUED) GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 K16 K14 L17 L16 R5 K13 U6 L6 U7 P7 L15 U8 P6 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
M20 N21 N19 N18 W6 N20 V7 V2 W8 Y8 M15 V9 P19 P3 P20 P18 N8 M14 D15 R19 R18 Y5
General-Purpose IOs module 1. Each GPIO pin can be used by either the DSP core or the MPU core. Control of each GPIO pin between the two cores is selected by the MPU via control registers. Each GPIO pin may also be configured to cause an interrupt to its respective core processor.
I/O
L14 K3 M17 L13 J6 M16 C12 M15 N17
Value sampled at power-up reset selects protocol on EMIFS interface. If 0 is sampled, protocol is non-address/data multiplexed. If 1 is sampled, protocol is address/data multiplexed.
I/O
I = Input, O = Output, Z = High-Impedance
December 2003 - Revised March 2004
SPRS231B
91
PRODUCT PREVIEW
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION MPU GENERAL-PURPOSE IO (MPUIOs) MPUIO15 MPUIO14 MPUIO13 MPUIO12 MPUIO11 MPUIO10 MPUIO9 MPUIO8 F13 J13 N14 D17 J17 T4 T9 U9 E16 P9 E17 F15 U9 C17 P9 MPUIO5 MPUIO4 MPUIO3 MPUIO2 MPUIO1 MPUIO0 N16 T4 M14 R6 L12 N15 P15 F14 U12 MPUIO7 MPUIO6 E19 L18 U20 E20 L19 W5 W10 V10 H14 W11 F19 G18 V10 D20 W11 T20 W5 T19 V8 N15 U19 V19 F18 R13 KEYBOARD MATRIX INTERFACE KB.C[7:0] P15 R16 F17 D16 E15 B17 C17 F14 K16 K14 L17 F13 D17 E16 E17 F15 V19 P15 G19 C21 E18 D19 D20 F18 M20 N21 N19 E19 E20 H14 F19 G18 Keyboard matrix column outputs. KB.Cx column outputs are used in conjunction with the KB.Rx row inputs to implement a 6 x 5 or 8 x 8 keyboard matrix. Keyboard matrix row inputs. KB.Rx row inputs are used in conjunction with the KB.Cx column outputs to implement a 6 x 5 or 8 x 8 keyboard matrix. O MPU general-purpose I/O. MPUIO pins may only be used by the MPU core. I/O TYPE
PRODUCT PREVIEW
KB.R[7:0]
I
LED PULSE GENERATOR (LPG) LED1 LED2 L13 M14 P18 T19 LED pulse generator output 1. LED1 produces a static or pulsing output used to drive an external LED indicator. LED pulse generator output 2. LED2 produces a static or pulsing output used to drive an external LED indicator. O O
PULSE-WIDTH TONE (PWT) AND PULSE-WIDTH LIGHT (PWL) INTERFACE PWL PWT
K15 K17
L14 M18
Pulse-width light output. The PWL output pin provides a pseudo-random modulated voltage output used for LCD or keypad backlighting. Pulse-width tone output. The PWT output pin provides a modulated output for use with an external buzzer.
O O
I = Input, O = Output, Z = High-Impedance
92
SPRS231B
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION GENERAL-PURPOSE TIMERS TIMER.EVENT3 TIMER.EVENT4 TIMER.EXTCLK TIMER.PWM2 TIMER.PWM1 TIMER.PWM0 L14 M17 L16 K16 K15 K17 P19 P20 N18 M20 L14 M18 Event capture input signal for GP timer 3 Event capture input signal for GP timer 4 Input clock for the GP timers PWM output of GP timer 2 PWM output of GP timer 1 PWM output of GP timer 0 I I I O O O TYPE
EMBEDDED TRACE MACROCELL (ETM) INTERFACE ETM.CLK ETM.PSTAT[5:0] G16 K13 M16 L13 J13 J12 K12 H16 H15 H17 J11 H13 J14 J16 J17 L15 H12 J15 N20 M14 P18 L18 L15 M19 J18 J19 J14 K18 K19 K15 K14 L19 M15 H19 ETM9 trace clock ETM9 trace pipe state bits O O
ETM.SYNC[1:0]
ETM9 trace synchronization bits DEVICE CLOCK PINS
O
CLK32K_IN CLK32K_OUT OSC32K_IN OSC32K_OUT SYS_CLK_IN SYS_CLK_OUT OSC1_IN
T11 U12 U11 U10 P5 F10 R2
P13 R13 V13 AA13 Y4 B15 Y2
32-kHz clock input. Digital CMOS 32-kHz clock input driven by an external 32-kHz oscillator if the internal 32-kHz oscillator is not used. 32-kHz clock output. Clock output reflecting the internal 32-kHz clock. 32-kHz crystal XI connection. Analog clock input to 32-kHz oscillator for use with external crystal. 32-kHz crystal XO connection. Analog output from 32-kHz oscillator for use with external crystal. System clock main input clock at 19.2-MHz or 12/13-MHz System clock can be output on this pin. Base crystal XI connection. Analog input to base oscillator for use with external crystal or to be driven by external 19.2-MHz or 12/13-MHz oscillator. Base crystal XO connection. Analog output from base oscillator for use with external 19.2-MHz or 12/13-MHz crystal. General-purpose clock output that can be configured to run at 12 or 13 MHz (depending on base oscillator frequency) or 48 MHz. BCLK can be configured to drive constantly or only when the BCLKREQ signal is asserted active-high. BCLK clock request. Active-high request input that allows an external device to request that BCLK be driven. General-purpose master clock output that may be configured to run at 12 or 13 MHz (depending on base oscillator frequency) or 48 MHz. MCLK can be configured to drive constantly or only when the MCLKREQ signal is asserted active-high. MCLK clock request. Active-high request input that allows an external device to request that MCLK be driven.
I O I O I O I
OSC1_OUT BCLK
P2 L10
W3 Y15
O O
BCLKREQ MCLK
R12 U3
W15 V5
I O
MCLKREQ
T7
R10
I
I = Input, O = Output, Z = High-Impedance
Embedded Trace Macrocell, ETM, and ETM9 are trademarks of ARM Limited in the EU and other countries. 93
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PRODUCT PREVIEW
ETM.D[7:0]
ETM9 trace packet bits
O
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# RESET LOGIC PINS PWRON_RESET MPU_RST N8 N14 R12 U20 Reset input to device. Active-low asynchronous reset input resets the entire OMAP5912 device. MPU reset input. Active-low asynchronous reset input resets the MPU core. NOTE: MPU_RST must meet minimum specified pulse width requirements and must be free of glitching to guard against potential operational issues. Reset output. Active-low output is asserted when RST_OUT is active (after synchronization). I I DESCRIPTION TYPE
RST_OUT
N12
AA20
O
INTERRUPTS AND MISCELLANEOUS CONTROL AND CONFIGURATION PINS MPU_BOOT H14 J20 MPU boot mode. When MPU_BOOT is low, the MPU boots internally from chip-select 0. When MPU_BOOT is high and if the device is an emulation device, the MPU externally boots from chip-select 3 of EMIFS. Protocol (address/data multiplexed or address/data non-multiplexed) is determined by the value on GPIO1. Battery power failure and external FIQ interrupt input. BFAIL can be used to gate certain input pins when battery power is low or failing. The pins that can be gated are configured via software. This pin can also optionally be used as an external FIQ interrupt source to the MPU. The function of this pin is configurable via software. External DMA request. EXT_DMA_REQ0 provides DMA request inputs which external devices can use to trigger system DMA transfers. The system DMA must be configured in software to respond to these external requests. External DMA request. EXT_DMA_REQ1 provides DMA request inputs which external devices may use to trigger system DMA transfers. The system DMA must be configured in software to respond to these external requests. Low-power request output. This active-high output indicates that the OMAP5912 device is in a LOW_PWR sleep mode. During reset and functional modes, LOW_PWR is driven low. This signal can be used to indicate a low-power state to external power management devices in a system, or it can be used as a chip-select to external SDRAM memory to minimize current consumption while the SDRAM is in self-refresh and the OMAP5912 device is in sleep mode. Output from ultra low-power device (ULPD) Active-low asynchronous reset signal if real-time clock (RTC) is used. RTC wake-up interrupt. RTC periodic interrupt to external power device to restart the main power supplies when RTC times out. External master request. If the base clock is provided by an external device instead of an on-chip oscillator, a high level on this output indicates to the external device that the clock must be driven. A low level indicates that the OMAP5912 device is in sleep mode and the 12- or 13-MHz external clock source is not necessary. A software-controllable reset or shutdown output to an external device OMAP5912 configuration input I
BFAIL/EXT_FIQ
T17
W19
I
PRODUCT PREVIEW
EXT_DMA_REQ0
L12
N15
I
EXT_DMA_REQ1
M14
T19
I
LOW_PWR
N16
T20
O
LOW_POWER RTC_ON_NOFF RTC_WAKE_INT EXT_MASTER_REQ
P4 P10 N9 T7
W4 Y12 W13 R10
O I O O
RST_HOST_OUT CONF
N9 R14
W13 V18
O I
I = Input, O = Output, Z = High-Impedance
94
SPRS231B
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Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# POWER SUPPLIES CVDD CVDD1 CVDD2 CVDD3 C11 K5 M7 T16 T3 H7 G9 G8 G10 H11 K11 J10 L9 P17 A15 M2 Y9 Y20 AA3 A3 A9 E2 B13 B20 J21 R20 W12 Y21 Core supply voltage. Supplies power to OMAP5912 core logic and low-voltage sections of I/O. Core supply voltage 1. Supplies power to OMAP5912 core logic. Core supply voltage 2. Supplies power to the MPU subsystem logic and memory. Core supply voltage 3. Supplies power to the DSP subsystem logic and memory. If the DSP system is not used, can be grounded after the isolation control in ULPD is set. Core supply voltage for the RTC. Supplies power to the RTC core logic. Can be connected to CVDD if the RTC is not used as a standalone. Analog supply voltage. Supplies power to the analog phase-locked loop (APLL) used to provide 48-MHz clock to peripherals such as USB, UART, or MMC/SD/SDIO peripherals. Note: The voltage to this supply pin must be kept as clean as possible to maximize performance by minimizing clock jitter. Core supply voltage for the digitally controlled delay element (calibration module) used to control read and write timings to external dual data rate (DDR) SDRAM. It is recommended that an RC (R = 10 , C = 100 nF) low-pass filter be implemented externally to filter switching noises. I/O supply voltage 1. Supplies power to the majority of peripheral I/O buffers. DVDD1 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 2. Supplies power to the internal USB transceiver buffers of USB port 0. DVDD2 can optionally be used for USB connect and disconnect detection by connecting DVDD2 to the power from the USB bus in the system. DVDD2 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 3. Supplies power to the MCSI2 and McBSP2 peripheral I/O buffers as well as to GPIO[9:8] I/O buffers. The DVDD3 supply can operate within a high-voltage or low-voltage range. DVDD3 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 4. Supplies power to the DDR/SDRAM interface I/O buffers. The DVDD4 supply can operate within a high-voltage or low-voltage range. DVDD4 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 5. Supplies power to the flash interface I/O buffers. The DVDD5 supply can operate within a high-voltage or low-voltage range. DVDD5 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 6. Supplies power to the MMC/SD1 interface I/O buffers. DVDD6 can be connected in common with the other DVDD supplies if the same operating voltage is desired. Power Power Power Power DESCRIPTION TYPE
CVDDRTC CVDDA
Power Power
DVDD1
C14 G12
A19 E21
Power
DVDD2
U2
AA2
Power
DVDD3
T6
Y7
Power
DVDD4
D6 D7 D8 D11
A5 A7 B10 B14
Power
DVDD5
B1 G1 L3
C2 H2 R1
Power
DVDD6
T10
AA11
Power
I = Input, O = Output, Z = High-Impedance
December 2003 - Revised March 2004
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PRODUCT PREVIEW
CVDDDLL
A9
A11
Power
Introduction
Table 2-5. Signal Description (Continued)
SIGNAL ZDY BALL# ZZG BALL# DESCRIPTION POWER SUPPLIES (CONTINUED) DVDD7 T13 Y16 I/O supply voltage 7. Supplies power to the McBSP3, MCSI1, UART, and USB port 1 I/O buffers. DVDD7 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 8. Supplies power to the camera interface (I/F) and embedded trace macrocell (ETM) I/O buffers. DVDD8 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage 9. Supplies power to the GPIO (except GPIO[9:8]), MPUIO, and MICROWIRE I/O buffers. DVDD9 can be connected in common with the other DVDD supplies if the same operating voltage is desired. I/O supply voltage for the RTC I/O. (RTC_ON_NOFF, RTC_WAKE_INT, CLK32K_IN, CLK32K_OUT, OSC32K_OUT, OSC32K_IN, PWRON_RESET). DVDDRTC can be connected in common with the other DVDD supplies if the same operating voltage is desired and the RTC is not used in standalone. A regulated supply is delivered by an embedded LDO to the DPLL macro(s).The regulated supply is available on the bond pad. A decoupling capacitor of 1 F must be connected externally between LDO.FILTER and the ground. Common ground for all core and I/O-Voltage supplies. Power TYPE
DVDD8
J15
L21
Power
DVDD9
M13
U21
Power
DVDDRTC
R10
V12
Power
PRODUCT PREVIEW
LDO.FILTER
H1
J1
Power
VSS
F6 E13 E5 G7 F12 K10 K9 H9 H10 M12 J9 R9 M6 K8 L11 N5 H8 G11 N13 L7
A13 A21 B1 B5 B7 B16 F20 G1 K2 K20 N1 P12 R21 U2 W20 Y3 Y13 AA1 AA7 AA21
Power
I = Input, O = Output, Z = High-Impedance
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Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3-1.
OMAP5912 32 Endianism Conversion TMS320C55x DSP (Instruction Cache, SARAM, DARAM, DMA, H/W Accelerators) DSP Public Peripheral Bus 16 DSP Private Peripherals Timers (3) Watchdog Timer Level 1/2 Interrupt Handlers DSP Public Peripherals McBSP1 (Audio PCM I/F) McBSP3 (Optical I/F) MCSI1 (Bluetooth Voice I/F) MCSI2 (Modem Voice) 16 DSP Public (Shared) Peripheral Bus MPU/DSP Shared Peripherals Mailbox MPU/DSP Static Shared 8 x GPTIMERS SPI UART1,2,3 I2C MMC/SDIO2 McBSP2 MPU/DSP Dynamic Shared GPIO1,2,3,4 32-kHz Synchro Counter
Compact Flash Boot ROM
DSP MMU
Endianism Conversion 16 32 MPU Bus MPU Interface 32 32 32 MPU Peripheral Bridge 32 MPU Public Peripheral Bus
32
Flash and SRAM
16
E M I F S E M I F F O C P - T1
16 SDRAM
System DMA Controller
32 MPU Public Peripherals USB Controllers SoSSI 32 OCP
O C P - T2
O C P - I MPU Private Peripheral Bus
MPU Private Peripherals Timers (3) Watchdog Timer Level 1/2 Interrupt Handlers Configuration Registers System DMA 32-kHz Watchdog LCD CONV
Frame Buffer
Switch GDD SSI VLYNQ MPU Core ARM926EJ-S (Instruction Cache, Data Cache, MMU) LCD I/F
32
32
ULPD Clock and Reset Management OSC OSC
MICROWIRE I/F Camera I/F RTC PWT PWL Keyboard I/F HDQ/1-Wire MMC/SDIO1 MPUIO LPG1,2 FAC QS Timer
JTAG/Emulation I/F
ETM9
16 12 MHz 32 kHz Clock Reset External Clock Requests
Figure 3-1. OMAP5912 Functional Block Diagram
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Memory Interface Traffic Controller (TC)
Functional Overview
3.1
Functional Block Diagram Features
The OMAP5912 device includes the following functional blocks: * ARM9TDMI-based (ARM926EJ-S) MPU core - - - - * * * 16K-byte instruction cache and 8K-byte data cache Memory Management Units (MMUs) with Translation Look-Aside Buffer (TLB) L1 16K-byte, four-way, set-associative instruction cache L1 8K-byte, four-way, set-associative data cache with buffer
MPU interrupt handler level 1 Embedded Trace Macrocell module, ETM version 2.a in a 13-bit mode configuration or in a 17-bit demultiplexed mode configuration C55x DSP subsystem - - - - - - - - - 48K-word single-access RAM (SARAM) (96K bytes) 32K-word dual-access RAM (DARAM) (64K bytes) 16K-word ROM (32K bytes) 24K-byte instruction cache Six-channel DMA controller Hardware Accelerators for DCT, iDCT, pixel interpolation, and motion estimation L1 cache (24K bytes) DSP interrupt handler level 1 in the C55x DSP core Embedded emulator interface through JTAG port
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* * *
DSP Memory Management Unit (MMU) configured by the MPU DSP level 2 interrupt handler, which enables connection to 16 additional interrupt lines outside OMAP through the DSP interrupt interface. The priority of each interrupt line is controlled by software. Four mailboxes for DSP/MPU communications. Each mailbox is implemented with 2 x 16-bit registers. When a write is done into a register by one processor, it generates an interrupt, released by the read access of the other processor. - - Two Read/Write accessible by MPU, read-only by the DSP Two Read/Write accessible by the DSP, read-only by the MPU
* *
External LCD controller support in addition to the OMAP LCD controller - LCD controller with its own tearing effect logic
Memory traffic controller - External memory interface slow (EMIFS). Connects to external device memories such as Flash and SRAM. This interface enables 16-bit data accesses and provides four chip-selects, each of which can support up to 128M bytes of address space with a 25-bit address bus. External memory interface fast (EMIFF). Connects to external dual data rate (DDR) SDRAM with 16-bit data accesses. It supports connection to a maximum of 128M bytes of SDRAM. The address width is 16 bits with two bank-selection bits. This provides interfacing with a maximum of 4 banks of 64M x 16-bit SDRAM memory with DDR capability.
-
* * *
Emulator interface through JTAG port Programmable DPLL Endianism conversion for DSP. The DSP uses big-endian format. The MPU and OMAP chip use little-endian format.
ARM9TDMI is a registered trademark of ARM Limited in the EU and other countries. 98
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*
MPU private peripherals (accessible only by the MPU) - - - - - - - Three 32-bit general-purpose timers Watchdog timer Level 1/Level 2 interrupt handlers Configuration register for pin-multiplexing and other device-level configurations CompactFlash controller LCD controller supporting monochrome panels or STN and TFT color panels LCDCONV to provide 18-bit (instead of 16-bit) to the LCD interface
*
DSP private peripherals (accessible only by the DSP) - - - Three 32-bit general-purpose timers Watchdog timer Level1/Level 2 interrupt handlers
*
MPU public peripherals (accessible by the MPU and the system DMA) - - - - - - - - - - - - - - - USB interface Display interface SoSSI Camera interface providing connectivity to CMOS image sensors Compact camera port MICROWIRE serial interface Real-time clock (RTC) module Pulse-width tone (PWT) Pulse-width light (PWL) Keyboard interface (6 x 5 or 8 x 8 matrix) HDQ/1-Wire interface for serial communication to battery management devices Multimedia card/secure digital (MMC/SDIO1) or SPI port Up to 16 MPU general-purpose I/Os (MPUIOs) LED pulse generator (LPG) Frame adjustment counter (FAC) 32-kHz OS timer
*
DSP public peripherals (accessible by: DSP, DSP DMA, and the MPU via the MPU interface ) - - Two multichannel buffered serial ports (McBSP1 and 3) Two multichannel serial interfaces (MCSI1 and 2)
*
MPU/DSP shared peripherals (controlling processor is selected by the MPU) - - - - Four mailboxes for interprocessor communications Eight general-purpose timers Serial port interface (SPI) Three UARTs (UART1 and UART3 have SIR mode for IrDA operation)
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PRODUCT PREVIEW
Functional Overview
- - - - - *
Inter-integrated circuit (I2C) multimode master and slave interface Multimedia card/secure digital (MMC/SDIO2) Multichannel buffered serial port (McBSP2) Up to 64 general-purpose I/O pins with interrupt capability to either processor 32-kHz synchro counter
MPU/DSP shared peripherals (accessible via OCP-T2 Port) - - VLYNQ interface SSI interface
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Functional Overview
3.2
MPU Memory Maps
3.2.1 MPU Global Memory Map
The MPU has a unified address space; therefore, the internal and external memories for program and data, as well as peripheral registers and configuration registers, are all accessed within the same address space. The MPU space is always addressed using byte addressing. Table 3-1 provides a high level illustration of the entire MPU addressable space. More details about the peripheral and configuration registers are provided in Section 3.2.2, MPU Subsystem Registers Memory Map.
Table 3-1. OMAP5912 MPU Global Memory Map
DEVICE NAME START ADDRESS (HEX) END ADDRESS (HEX) EMIFS CS0 Boot ROM Reserved Boot ROM Reserved NOR FLASH CS1 NOR FLASH CS2 NOR FLASH CS3 NOR FLASH 0000 0000 0000 0000 0001 0000 0004 0000 0200 0000 0400 0000 0400 0000 0800 0000 0800 0000 0C00 0000 0C00 0000 03FF FFFF 0000 FFFF 0003 FFFF 01FF FFFF 03FF FFFF 07FF FFFF 07FF FFFF 0BFF FFFF 0BFF FFFF 0FFF FFFF 0FFF FFFF EMIFF SDRAM External Reserved Frame Buffer Reserved SSI Mapping GDD Mapping VLYNQ Config Reserved VLYNQ Config Reserved 1000 0000 1800 0000 2000 0000 2003 E800 3000 0000 3000 1000 3000 2000 3000 2200 3100 0000 3500 0000 17FF FFFF 1FFF FFFF L3 OCP TI 2003 E7FF 2FFF FFFF L3 OCP T2 3000 0FFF 3000 1FFF 3000 21FF 30FF FFFF 34FF FFFF 7FFF FFFF 64M bytes 4K bytes 4K bytes 512 bytes Cannot use simultaneously with GDD/SSI 250K bytes 32-bit EX/R/W 128M bytes 16-bit EX/R/W 32M bytes 64M bytes 64M bytes 64M bytes 64M bytes 64M bytes 64M bytes 8/16/32-bit EX/R/W 16-bit or 32-bit organized 8/16/32-bit EX/R/W 16-bit or 32-bit organized 8/16/32-bit EX/R/W 16-bit or 32-bit organized 8/16/32-bit EX/R/W 16-bit or 32-bit organized 64M bytes 64K bytes 192K bytes 32-bit Ex/R 32-bit Ex/R SIZE DATA ACCESS TYPE COMMENT
NOTE: CS1 and CS2 can be split to provide up to four chip selects. In this case, each chip select can support 32M bytes of NOR Flash memory. CS1a CS1b CS2a CS2b 0x0400 0000 0x0600 0000 0x0800 0000 0x0A00 0000 0x05FF FFFF 0x07FF FFFF 0x09FF FFFF 0x0BFF FFFF 32M 32M 32M 32M bytes bytes bytes bytes
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Functional Overview
Table 3-1. OMAP5912 MPU Global Memory Map (Continued)
DEVICE NAME START ADDRESS (HEX) END ADDRESS (HEX) SIZE DATA ACCESS TYPE COMMENT
DSP MPUI Interface MPUI memory+ MPUI peripheral Reserved Reserved OMAP5912 Peripherals Reserved E000 0000 E102 0000 F000 0000 FFFB 0000 FFFF 0000 E101 FFFF EFFF FFFF Peripheral and Control Registers FFFA FFFF FFFE FFFF FFFF FFFF Reserved Memory Space
NOTE: CS1 and CS2 can be split to provide up to four chip selects. In this case, each chip select can support 32M bytes of NOR Flash memory. CS1a CS1b CS2a CS2b 0x0400 0000 0x0600 0000 0x0800 0000 0x0A00 0000 0x05FF FFFF 0x07FF FFFF 0x09FF FFFF 0x0BFF FFFF 32M 32M 32M 32M bytes bytes bytes bytes
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Functional Overview
3.2.2 MPU Subsystem Registers Memory Map
The MPU accesses peripheral and configuration registers in the same way that internal and external memory are accessed. The following tables specify the MPU base addresses where each set of registers is accessed. All accesses to these registers must utilize the appropriate access width (8-, 16-, or 32-bit-wide accesses) as indicated in the tables. Accessing registers with the incorrect access width are illegal. WARNING: Access to Reserved areas is illegal.
3.2.2.1
MPU Private Peripheral Registers
The MPU private peripheral registers include the following: * * * * * * * * * MPU Level 2 Interrupt Handler Registers LCDCONV Registers LCD Controller Registers MPU Timer1 Registers MPU Timer2 Registers MPU Timer3 Registers MPU Watchdog Timer Registers MPU Level 1 Interrupt Handler Registers System DMA Controller Registers
Table 3-2. MPU Level 2 Interrupt Handler Registers
BYTE ADDRESS FFFE:0000 FFFE:0004 FFFE:0008 FFFE:000C FFFE:0010 FFFE:0014 FFFE:0018 FFFE:001C FFFE:0020 FFFE:0024 FFFE:0028 FFFE:002C FFFE:0030 FFFE:0034 FFFE:0038 FFFE:003C FFFE:0040 FFFE:0044 REGISTER NAME MPU_L2_ITR MPU_L2_MIR RESERVED RESERVED MPU_L2_SIR_IRQ MPU_L2_SIR_FIQ MPU_L2_CONTROL MPU_L2_ILR0 MPU_L2_ILR1 MPU_L2_ILR2 MPU_L2_ILR3 MPU_L2_ILR4 MPU_L2_ILR5 MPU_L2_ILR6 MPU_L2_ILR7 MPU_L2_ILR8 MPU_L2_ILR9 MPU_L2_ILR10 Interrupt Register Interrupt Mask Register Reserved Reserved Interrupt Encoded Source (IRQ) Register Interupt Encoded Source (FIQ) Register Interrupt Control Register Interrupt Priority Level For IRQ 0 Register Interrupt Priority Level For IRQ 1 Register Interrupt Priority Level For IRQ 2 Register Interrupt Priority Level For IRQ 3 Register Interrupt Priority Level For IRQ 4 Register Interrupt Priority Level For IRQ 5 Register Interrupt Priority Level For IRQ 6 Register Interrupt Priority Level For IRQ 7 Register Interrupt Priority Level For IRQ 8 Register Interrupt Priority Level For IRQ 9 Register Interrupt Priority Level For IRQ 10 Register 32 32 32 32 32 32 32 32 32 32 32 32 32 32 R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h DESCRIPTION ACCESS WIDTH 32 32 ACCESS TYPE R/W R/W RESET VALUE 0000 0000h FFFFFFFFh
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Functional Overview
Table 3-2. MPU Level 2 Interrupt Handler Registers (Continued)
BYTE ADDRESS FFFE:0048 FFFE:004C FFFE:0050 FFFE:0054 FFFE:0058 FFFE:005C FFFE:0060 FFFE:0064 FFFE:0068 FFFE:006C FFFE:0070 FFFE:0074 FFFE:0078 FFFE:007C REGISTER NAME MPU_L2_ILR11 MPU_L2_ILR12 MPU_L2_ILR13 MPU_L2_ILR14 MPU_L2_ILR15 MPU_L2_ILR16 MPU_L2_ILR17 MPU_L2_ILR18 MPU_L2_ILR19 MPU_L2_ILR20 MPU_L2_ILR21 MPU_L2_ILR22 MPU_L2_ILR23 MPU_L2_ILR24 MPU_L2_ILR25 MPU_L2_ILR26 MPU_L2_ILR27 MPU_L2_ILR28 MPU_L2_ILR29 MPU_L2_ILR30 MPU_L2_ILR31 MPU_L2_ISR MPU_L2_STATUS MPU_L2_OCP_CFG MPU_L2_INTH_REV DESCRIPTION Interrupt Priority Level For IRQ 11 Register Interrupt Priority Level For IRQ 12 Register Interrupt Priority Level For IRQ 13 Register Interrupt Priority Level For IRQ 14 Register Interrupt Priority Level For IRQ 15 Register Interrupt Priority Level For IRQ 16 Register Interrupt Priority Level For IRQ 17 Register Interrupt Priority Level For IRQ 18 Register Interrupt Priority Level For IRQ 19 Register Interrupt Priority Level For IRQ 20 Register Interrupt Priority Level For IRQ 21 Register Interrupt Priority Level For IRQ 22 Register Interrupt Priority Level For IRQ 23 Register Interrupt Priority Level For IRQ 24 Register Interrupt Priority Level For IRQ 25 Register Interrupt Priority Level For IRQ 26 Register Interrupt Priority Level For IRQ 27 Register Interrupt Priority Level For IRQ 28 Register Interrupt Priority Level For IRQ 29 Register Interrupt Priority Level For IRQ 30 Register Interrupt Priority Level For IRQ 31 Register Software Interrupt Set Register Status Register OCP Configuration Register Interrupt Controller Revision ID ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
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FFFE:0080 FFFE:0084 FFFE:0088 FFFE:008C FFFE:0090 FFFE:0094 FFFE:0098 FFFE:009C FFFE:00A0 FFFE:00A4 FFFE:00A8
Table 3-3. LCDCONV Registers
BYTE ADDRESS REGISTER NAME DESCRIPTION R Look-up Table Register File B Look-up Table Register File G Look-up Table Register File Control Register Device Revision Register ACCESS WIDTH 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R RESET VALUE undefined undefined undefined 0000h undefined
FFFE:3000 - LCDCONV_R_LOOK_UP FFFE:301F FFFE:3020 - LCDCONV_B_LOOK_UP FFFE:303F FFFE:3040- FFFE:307F FFFE:3080 FFFE:3084 LCDCONV_G_LOOK_UP LCDCONV_CONTROL LCDCONV_DEV_REV
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Functional Overview
Table 3-4. LCD Controller Registers
BYTE ADDRESS FFFE:C000 FFFE:C004 FFFE:C008 FFFE:C00C FFFE:C010 FFFE:C014 FFFE:C018 FFFE:C01C REGISTER NAME LCD_CONTROL LCD_TIMING0 LCD_TIMING1 LCD_TIMING2 LCD_STATUS LCD_SUBPANEL LCD_LINEINT LCD_DISPLAYSTATUS DESCRIPTION LCD Control Register LCD Timing0 Register LCD Timing1 Register LCD TIming2 Register LCD Status Register LCD Subpanel Display Register LCD Line Interrupt Register LCD Display Status Register ACCESS WIDTH 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE xx00 0000h 0000 000Fh 0000 0000h xx00 0000h xxxx xxx0h xx00 0000h xxxx xx00h xxxx x3FFh
Table 3-5. MPU Timer1 Registers
BYTE ADDRESS FFFE:C500 FFFE:C504 FFFE:C508 REGISTER NAME MPU_CNTL_TIMER1 MPU_LOAD_TIMER1 MPU_READ_TIMER1 DESCRIPTION MPU Timer1 Control Register MPU Timer1 Load Register MPU Timer1 Read Register ACCESS WIDTH 32 32 32 ACCESS TYPE R/W W R RESET VALUE 0000 0000h undefined
Table 3-6. MPU Timer2 Registers
BYTE ADDRESS FFFE:C600 FFFE:C604 FFFE:C608 REGISTER NAME MPU_CNTL_TIMER2 MPU_LOAD_TIMER2 MPU_READ_TIMER2 DESCRIPTION MPU Timer2 Control Register MPU Timer2 Load Register MPU Timer2 Read Register ACCESS WIDTH 32 32 32 ACCESS TYPE R/W W R RESET VALUE 0000 0000h undefined undefined
Table 3-7. MPU Timer3 Registers
BYTE ADDRESS FFFE:C700 FFFE:C704 FFFE:C708 REGISTER NAME MPU_CNTL_TIMER3 MPU_LOAD_TIME3 MPU_READ_TIMER3 DESCRIPTION MPU Timer3 Control Register MPU Timer3 Load Register MPU Timer3 Read Register ACCESS WIDTH 32 32 32 ACCESS TYPE R/W W R RESET VALUE 0000 0000h undefined undefined
Table 3-8. MPU Watchdog Timer Registers
BYTE ADDRESS FFFE:C800 FFFE:C804 FFFE:C804 FFFE:C808 REGISTER NAME MPU_WDT_CNTL_TIMER MPU_WDT_LOAD_TIMER MPU_WDT_READ_TIMER MPU_WDT_TIMER_MODE DESCRIPTION MPU Watchdog Timer Control Register MPU Watchdog Timer Load Register MPU Watchdog Timer Read Register MPU Watchdog Timer Mode Register ACCESS WIDTH 32 32 32 32 ACCESS TYPE R/W W R R/W RESET VALUE 0000 0E02h xxxx FFFFh xxxx FFFFh 0000 8000h
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PRODUCT PREVIEW
undefined
Functional Overview
Table 3-9. MPU Level 1 Interrupt Handler Registers
BYTE ADDRESS FFFE:CB00 FFFE:CB04 FFFE:CB08 FFFE:CB0C FFFE:CB10 FFFE:CB14 FFFE:CB18 FFFE:CB1C FFFE:CB20 FFFE:CB24 FFFE:CB28 FFFE:CB2C FFFE:CB30 FFFE:CB34 FFFE:CB38 FFFE:CB3C FFFE:CB40 FFFE:CB44 FFFE:CB48 FFFE:CB4C FFFE:CB50 FFFE:CB54 FFFE:CB58 FFFE:CB5C FFFE:CB60 FFFE:CB64 FFFE:CB68 FFFE:CB6C FFFE:CB70 FFFE:CB74 FFFE:CB78 FFFE:CB7C FFFE:CB80 FFFE:CB84 FFFE:CB88 FFFE:CB8C FFFE:CB90 FFFE:CB94 FFFE:CB98 FFFE:C9C FFFE:CBA0 REGISTER NAME MPU_L1_ITR MPU_L1_MIR RESERVED RESERVED MPU_L1_SIR_IRQ_CODE MPU_L1_SIR_FIQ_CODE MPU_L1_CONTROL MPU_L1_ILR0 MPU_L1_ILR1 MPU_L1_ILR2 MPU_L1_ILR3 MPU_L1_ILR4 MPU_L1_ILR5 MPU_L1_ILR6 MPU_L1_ILR7 MPU_L1_ILR8 MPU_L1_ILR9 MPU_L1_ILR10 MPU_L1_ILR11 MPU_L1_ILR12 MPU_L1_ILR13 MPU_L1_ILR14 MPU_L1_ILR15 MPU_L1_ILR16 MPU_L1_ILR17 MPU_L1_ILR18 MPU_L1_ILR19 MPU_L1_ILR20 MPU_L1_ILR21 MPU_L1_ILR22 MPU_L1_ILR23 MPU_L1_ILR24 MPU_L1_ILR25 MPU_L1_ILR26 MPU_L1_ILR27 MPU_L1_ILR28 MPU_L1_ILR29 MPU_L1_ILR30 MPU_L1_ILR31 MPU_L1_ISR MPU_L1_ENHANCED_CNTL DESCRIPTION Interrupt Register Interrupt Mask Register Reserved Reserved Interrupt Encoded Source (IRQ) Register Interupt Encoded Source (FIQ) Register Interrupt Control Register Interrupt Priority Level For IRQ 0 Register Interrupt Priority Level For IRQ 1 Register Interrupt Priority Level For IRQ 2 Register Interrupt Priority Level For IRQ 3 Register Interrupt Priority Level For IRQ 4 Register Interrupt Priority Level For IRQ 5 Register Interrupt Priority Level For IRQ 6 Register Interrupt Priority Level For IRQ 7 Register Interrupt Priority Level For IRQ 8 Register Interrupt Priority Level For IRQ 9 Register Interrupt Priority Level For IRQ 10 Register Interrupt Priority Level For IRQ 11 Register Interrupt Priority Level For IRQ 12 Register Interrupt Priority Level For IRQ 13 Register Interrupt Priority Level For IRQ 14 Register Interrupt Priority Level For IRQ 15 Register Interrupt Priority Level For IRQ 16 Register Interrupt Priority Level For IRQ 17 Register Interrupt Priority Level For IRQ 18 Register Interrupt Priority Level For IRQ 19 Register Interrupt Priority Level For IRQ 20 Register Interrupt Priority Level For IRQ 21 Register Interrupt Priority Level For IRQ 22 Register Interrupt Priority Level For IRQ 23 Register Interrupt Priority Level For IRQ 24 Register Interrupt Priority Level For IRQ 25 Register Interrupt Priority Level For IRQ 26 Register Interrupt Priority Level For IRQ 27 Register Interrupt Priority Level For IRQ 28 Register Interrupt Priority Level For IRQ 29 Register Interrupt Priority Level For IRQ 30 Register Interrupt Priority Level For IRQ 31 Register Interrupt Priority Level For IRQ 0 Register Enhanced Control Register 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h ACCESS WIDTH 32 32 ACCESS TYPE R/W R/W RESET VALUE 0000 0000h FFFF FFFFh
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Functional Overview
Table 3-10. System DMA Controller Registers
BYTE ADDRESS TBD TBD REGISTER NAME TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
3.2.2.2
* * * * * * * * * * * * * * *
MPU Public Peripheral Registers
The MPU public peripheral registers include the following: USB On-the-Go (OTG) Registers MICROWIRE Registers USB Client Registers Real-Time Clock (RTC) Registers MPUIO (Keyboard Included) Registers Pulse Width Light (PWL) Registers
MMC/SDIO1 Registers OS Timer 32-kHz Registers USB Host Registers Frame Adjustment Counter (FAC) Registers Specially Optimized Screen Interface (SoSSI) Registers HDQ/1-Wire Interface Registers LED Pulse Generator 1 (LPG1) Registers LED Pulse Generator 2 (LPG2) Registers
Table 3-11. USB On-the-Go (OTG) Registers
BYTE ADDRESS FFFB:0700 FFFB:0704 FFFB:0708 FFFB:070C FFFB:0710 FFFB:0714 FFFB:0718 FFFB:0720 FFFB:07FC REGISTER NAME USB_OTG_REV USB_OTG_SYSCON1 USB_OTG_SYSCON2 USB_OTG_CTRL USB_OTG_IRQ_EN USB_OTG_IRQ_SRC USB_OTG_OUTCTRL USB_OTG_TEST USB_OTG_VC DESCRIPTION USB On The Go Revision Number USB On The Go Configuration Register 1 USB On The Go Configuration Register 2 USB On The Go Control Register USB On The Go Interrupt Enable Register USB On The Go Interrtup Status Register USB On The Go Output Pins Control Register USB On The Go Test Register USB On The Go Vendor Code Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 ACCESS TYPE R R/W R/W R/W R/W R/W R/W R/W R RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h undefined
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Pulse Width Tone (PWT) Registers
Functional Overview
Table 3-12. MICROWIRE Registers
BYTE ADDRESS FFFB:3000 FFFB:3000 FFFB:3004 FFFB:3008 FFFB:300C FFFB:3010 FFFB:3014 FFFB:3018 REGISTER NAME MWIRE_RDR MWIRE_TDR MWIRE_CSR MWIRE_SR1 MWIRE_SR2 MWIRE_SR3 MWIRE_SR4 MWIRE_SR5 DESCRIPTION MICROWIRE Receive Data Register MICROWIRE Transmit Data Register MICROWIRE Control And Status Register MICROWIRE Setup Register For CS0 And CS1 MICROWIRE Setup Register For CS2 And CS3 MICROWIRE Setup Register For Internal Clock MICROWIRE Setup Register For Clock Polarity MICROWIRE Setup Register For Transmit Mode ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE R W R/W R/W R/W R/W R/W R/W RESET VALUE undefined undefined undefined undefined undefined undefined undefined 0000h
Table 3-13. USB Client Registers
BYTE ADDRESS TBD REGISTER NAME TBD TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
PRODUCT PREVIEW
Table 3-14. Real-Time Clock (RTC) Registers
BYTE ADDRESS FFFB:4800 FFFB:4804 FFFB:4808 FFFB:480C FFFB:4810 FFFB:4814 FFFB:4818 FFFB:481C FFFB:4820 FFFB:4824 FFFB:4828 FFFB:482C FFFB:4830 FFFB:4834 FFFB:4838 - FFFB:483F FFFB:4840 FFFB:4844 FFFB:4848 FFFB:484C FFFB:4850 FFFB:4854 RTC_CTRL_REG RTC_STATUS_REG RTC_INTERRUPTS_REG RTC_COMP_LSB_REG RTC_COMP_MSB_REG RTC_OSC_REG ALARM_SECONDS_REG ALARM_MINUTES_REG ALARM_HOURS_REG ALARM_DAYS_REG ALARM_MONTHS_REG ALARM_YEARS_REG REGISTER NAME SECONDS_REG MINUTES_REG HOURS_REG DAYS_REG MONTHS_REG YEARS_REG WEEK_REG DESCRIPTION RTC Seconds Register RTC Minutes Register RTC Hours Register RTC Days Register RTC Months Register RTC Years Register RTC Weeks Register Reserved RTC Alarm Seconds Register RTC Alarm Minutes Register RTC Alarm Hours Register RTC Alarm Days Register RTC Alarm Months Register RTC Alarm Years Register Reserved RTC Control Register RTC Status Register RTC Interrupts Register RTC Compensation LSB Register RTC Compensation MSB Register RTC Oscillator Register 8 8 8 8 8 8 R/W R/W R/W R/W RW RW 00h 00h 00h 00h 00h 0Bh 8 8 8 8 8 8 R/W R/W R/W R/W R/W R/W 00h 00h 00h 01h 01h 00h ACCESS WIDTH 8 8 8 8 8 8 8 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W RESET VALUE 00h 00h 00h 01h 01h 00h 00h
108
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Functional Overview
Table 3-15. MPUIO (Keyboard) Registers
BYTE ADDRESS FFFB:5000 FFFB:5004 FFFB:5008 FFFB:5010 FFFB:5014 FFFB:5018 FFFB:501C FFFB:5020 FFFB:5024 FFFB:5028 FFFB:502C FFFB:5030 FFFB:5034 REGISTER NAME MPUIO_INPUT_LATCH MPUIO_OUTPUT MPUIO_IO_CNTL MPUIO_KBD_LATCH MPUIO_KBC MPUIO_GPIO_EVENT MPUIO_GPIO_EDGE MPUIO_KBD_INT MPUIO_GPIO_INT MPUIO_KBD_MASKIT MPUIO_GPIO_MASKIT MPUIO_GPIO_DBNC MPUIO_GPIO_LATCH DESCRIPTION MPUIO General Purpose Input Register MPUIO General Purpose Output Register MPUIO In/Out Control Register for General-Purpose I/O MPUIO Keyboard Row Input Register MPUIO Keyboard Column Ouput Register MPUIO GPIO Event Mode Register MPUIO GPIO Interrupt Edge Register MPUIO Keyboard Interrupt Register MPUIO GPIO Interrupt Register MPUIO Keyboard Interrupt Mask Register MPUIO GPIO Interrupt Mask Register MPUIO GPIO Debouncing Register MPUIO GPIO Latch Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R R/W R/W R R/W R/W R/W R R R/W R/W R/W R RESET VALUE 0000h 0000h FFFFh FFFFh FF00h 0FE0h 0000h FFFFh 0000h FFFEh 0000h EF00h 0000h
Table 3-16. Pulse Width Light (PWL) Registers
BYTE ADDRESS FFFB:5800 FFFB:5804 REGISTER NAME PWL_LEVEL PWL_CONTROL DESCRIPTION PWL Level Register PWL Control Register ACCESS WIDTH 8 8 ACCESS TYPE R/W R/W RESET VALUE 00h 00h
Table 3-17. Pulse Width Tone (PWT) Registers
BYTE ADDRESS FFFB:6000 FFFB:6004 FFFB:6008 REGISTER NAME PWT_FRC PWT_VRC PWT_GCR DESCRIPTION PWT Frequency Control Register PWT Volume Control Register PWT General Control Register ACCESS WIDTH 8 8 8 ACCESS TYPE R/W R/W R/W RESET VALUE 00h 00h 00h
Table 3-18. MMC/SDIO1 Registers
BYTE ADDRESS FFFB:7800 FFFB:7804 FFFB:7808 FFFB:780C FFFB:7810 FFFB:7814 FFFB:7818 FFFB:781C FFFB:7820 FFFB:7824 FFFB:7828 FFFB:782C REGISTER NAME MPU_MMC_CMD MPU_MMC_ARGL MPU_MMC_ARGH MPU_MMC_CON MPU_MMC_STAT MPU_MMC_IE MPU_MMC_CTO MPU_MMC_DTO MPU_MMC_DATA MPU_MMC_BLEN MPU_MMC_NBLK MPU_MMC_BUF DESCRIPTION MMC Command Register MMC Argument Register Low MMC Argument Register High MMC Module Configuration Register MMC Module Status Register MMC System Interrupt Enable Register MMC Command Time-Out Register MMC Data Read Time-Out Register MMC Data Access Register MMC Block Length Register MMC Numberf of Blocks Register MMC Buffer Configuration Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Functional Overview
Table 3-18. MMC/SDIO1 Registers (Continued)
BYTE ADDRESS FFFB:7830 FFFB:7834 FFFB:7838 FFFB:783C FFFB:7840 FFFB:7844 FFFB:7848 FFFB:784C FFFB:7850 FFFB:7854 FFFB:7858 FFFB:785C FFFB:7860 FFFB:7864 REGISTER NAME MPU_MMC_SPI MPU_MMC_SDIO MPU_MMC_SYST MPU_MMC_REV MPU_MMC_RSP0 MPU_MMC_RSP1 MPU_MMC_RSP2 MPU_MMC_RSP3 MPU_MMC_RSP4 MPU_MMC_RSP5 MPU_MMC_RSP6 MPU_MMC_RSP7 MPU_MMC_IOSR MPU_MMC_SYSC MPU_MMC_SYSS DESCRIPTION MMC SPI Configuration Register MMC SDIO Configuration Register MMC System Test Register MMC Module Revision Register MMC Command Response Register 0 MMC Command Response Register 1 MMC Command Response Register 2 MMC Command Response Register 3 MMC Command Response Register 4 MMC Command Response Register 5 MMC Command Response Register 6 MMC Command Response Register 7 MMC Command Response IOSR Register MMC System Control Register MMC System Status Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R R R R R R R R R R/W R/W R RESET VALUE 0000h 0000h 0000h undefined 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
PRODUCT PREVIEW
FFFB:7868
Table 3-19. OS Timer 32-kHz Registers
BYTE ADDRESS FFFB:9000 FFFB:9004 FFFB:9008 REGISTER NAME OS_TIMER_TICK_VAL OS_TIMER_TICK_CNTR OS_TIMER_CTRL DESCRIPTION OS Timer 32K Tick Value Register OS TIimer 32k Tick Counter Register OS Timer 32k Timer Control Register ACCESS WIDTH 32 32 32 ACCESS TYPE R/W R R/W RESET VALUE 00FF FFFFh 00FF FFFFh 0000 0008h
Table 3-20. USB Host Registers
BYTE ADDRESS TBD REGISTER NAME TBD TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
Table 3-21. Frame Adjustment Counter (FAC) Registers
BYTE ADDRESS FFFB:A800 FFFB:A810 FFFB:A814 FFFB:A804 FFFB:A808 FFFB:A80C REGISTER NAME FAC_CNT FAC_SYNC_CNT FAC_START_CNT FAC_CNT_RSLT FAC_CTRL FAC_STATUS DESCRIPTION FAC Frame Adjustment Reference Counter Register FAC Sync Counter Register FAC Start Counter Register FAC Frame Starter Count Register FAC Control Register FAC Status Register ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE R/W R R R R/W R RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h
110
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Functional Overview
Table 3-22. Specially Optimized Screen Interface (SoSSI) Registers
BYTE ADDRESS FFFB:AC00 FFFB:AC04 FFFB:AC08 FFFB:AC0C FFFB:AC10 FFFB:AC14 FFFB:AC18 FFFB:AC1C FFFB:AC20 REGISTER NAME SOSSI_IDENT SOSSI_INIT1 SOSSI_INIT2 SOSSI_INIT3 SOSSI_FIFO SOSSI_REOTABLE SOSSI_TEARING SOSSI_INIT1B SOSSI_FIFOB DESCRIPTION SoSSI Identification Register SoSSI Timing For Display Register SoSSI Main Control Register SoSSI Main Control Register SoSSI FIFO Register SoSSI Reordering Table Register SoSSI Tearing Effect Register SoSSI Part of INIT1 Register SoSSI Part of FIFO Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W W RESET VALUE 0000 0000h C000 0000h 0000 000Ch 0000 0047h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Table 3-23. HDQ/1-Wire Interface Registers
BYTE ADDRESS FFFB:C000 FFFB:C004 FFFB:C008 FFFB:C00C REGISTER NAME HDQ_TX_DATA HDQ_RX_BUF HDQ_CNTL_STAT HDQ_INT_STAT DESCRIPTION HDQ Transmit Register HDQ Receive Buffer Register HDQ Control and Status Register HDQ Interrupt Status Register ACCESS WIDTH 32 32 32 32 ACCESS TYPE R/W R R/W R RESET VALUE
0000 0000h 0000 0000h 0000 0000h
Table 3-24. LED Pulse Generator 1 (LPG1) Registers
BYTE ADDRESS FFFB:D000 FFFB:D004 REGISTER NAME LPG1_CNTL LPG1_PWR_MNGT DESCRIPTION LPG1 Control Register LPG1 Power Mangement Register ACCESS WIDTH 8 8 ACCESS TYPE R/W R/W RESET VALUE 00h 00h
Table 3-25. LED Pulse Generator 2 (LPG2) Registers
BYTE ADDRESS FFFB:D800 FFFB:D804 REGISTER NAME LPG2_CNTL LPG2_PWR_MNGT DESCRIPTION LPG2 Control Register LPG2 Power Mangement Register ACCESS WIDTH 8 8 ACCESS TYPE R/W R/W RESET VALUE 00h 00h
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PRODUCT PREVIEW
0000 0000h
Functional Overview
3.2.2.3
* * * * * * * * * * * * * * * * * * * * *
MPU/DSP Shared Peripheral Registers
The MPU public peripheral registers include the following: UART1 Registers UART2 Registers SPI1 Registers McBSP2 Registers General-Purpose Timer 1 Registers General-Purpose Timer 2 Registers General-Purpose Timer 3 Registers General-Purpose Timer 4 Registers General-Purpose Timer 5 Registers I2C1 Registers General-Purpose Timer 6 Registers General-Purpose Timer 7 Registers MMC/SDIO2 Registers UART 3 Registers MPU GPIO3 Registers MPU GPIO4 Registers 32-kHz Synchro Count Registers General-Purpose Timer 8 Registers MPU GPIO1 Registers MPU GPIO2 Registers MPU/DSP Shared Mailbox Registers
PRODUCT PREVIEW
112
SPRS231B
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Functional Overview
Table 3-26. UART1 Registers
DSP WORD ADDRESS 0x00 8000h 0x00 8000h 0x00 8000h 0x00 8001h 0x00 8001h 0x00 8002h 0x00 8002h 0x00 8002h 0x00 8003h 0x00 8004h 0x00 8004h 0x00 8005h 0x00 8005h 0x00 8006h 0x00 8006h 0x00 8006h 0x00 8007h 0x00 8007h 0x00 8007h 0x00 8008h 0x00 8009h 0x00 800Ah 0x00 800Ah 0x00 800Bh 0x00 800Bh 0x00 800Ch 0x00 800Ch 0x00 800Dh 0x00 800Dh 0x00 800Eh 0x00 800Eh 0x00 800Fh 0x00 8010h 0x00 8011h 0x00 8012h 0x00 8013h 0x00 8014h 0x00 8015h 0x00 8016h 0x00 8017h MPU BYTE ADDRESS FFFB:0000 FFFB:0000 FFFB:0000 FFFB:0004 FFFB:0004 FFFB:0008 FFFB:0008 FFFB:0008 FFFB:000C FFFB:0010 FFFB:0010 FFFB:0014 FFFB:0014 FFFB:0018 FFFB:0018 FFFB:0018 FFFB:001C FFFB:001C FFFB:001C FFFB:0020 FFFB:0024 FFFB:0028 FFFB:0028 FFFB:002C FFFB:002C FFFB:0030 FFFB:0030 FFFB:0034 FFFB:0034 FFFB:0038 FFFB:0038 FFFB:003C FFFB:0040 FFFB:0044 FFFB:0048 FFFB:004C FFFB:0050 FFFB:0054 FFFB:0058 FFFB:005C UART1_MVR UART1_SYSC UART1_SYSS UART1_WER REGISTER NAME UART1_RHR UART1_THR UART1_DLL UART1_IER UART1_DLH UART1_IIR UART1_FCR UART1_EFR UART1_LCR UART1_MCR UART1_XON1 UART1_LSR UART1_XON2 UART1_MSR UART1_TCR UART1_XOFF1 UART1_SPR UART1_TLR UART1_XOFF2 UART1_MDR1 UART1_MDR2 UART1_SFLSR UART1_TXFLL UART1_RESUME UART1_TXFLH UART1_SFREGL UART1_RXFLL UART1_SFREGH UART1_RXFLH UART1_UASR UART1_BLR UART1_ACREG UART1_SCR UART1_SSR UART1_EBLR DESCRIPTION UART1 receive holding register UART1 transmit holding register UART1 divisor latch low register UART1 interrupt enable register UART1 divisor latch high register UART1 interrupt identification register UART1 FIFO control register UART1 enhanced feature register UART1 line control register UART1 modem control register UART1 XON1 register UART1 mode register UART1 XON2 register UART1 modem status register UART1 transmission control register UART1 XOFF1 register UART1 scratchpad register UART1 trigger level register UART1 XOFF2 register UART1 mode definition 1 register UART1 mode definition register 2 UART1 status FIFO line status register UART1 transmit frame length low UART1 resume register UART1 transmit frame length high UART1 status FIFO low register UART1 receive frame length low UART1 status FIFO high register UART1 receive frame length high UART1 autobauding status register UART1 BOF control register UART1 auxiliary control register UART1 supplementary control register UART1 supplementary status register UART1 BOF length register Reserved UART1 module version register UART1 system configuration register UART1 system status register UART1 wake-up enable register 8 8 8 8 R R/W R/W R/W - 00h 00h 7Fh ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W R/W R/W R/W R W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R W R W R W R W R R/W R/W R/W R R/W RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h 00h 0Fh 00h 00h 00h 00h 07h 00h 00h 00h 00h 00h Undefined 00h Undefined 00h 00h 40h 00h 00h 00h 00h Undefined
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PRODUCT PREVIEW
Functional Overview
Table 3-27. UART2 Registers
DSP WORD ADDRESS 0x00 8400h 0x00 8400h 0x00 8400h 0x00 8401h 0x00 8401h 0x00 8402h 0x00 8402h 0x00 8402h 0x00 8403h 0x00 8404h 0x00 8404h 0x00 8405h 0x00 8405h 0x00 8406h 0x00 8406h 0x00 8406h 0x00 8407h 0x00 8407h 0x00 8407h 0x00 8408h 0x00 8409h 0x00 840Ah 0x00 840Ah 0x00 840Bh 0x00 840Bh 0x00 840Ch 0x00 840Ch 0x00 840Dh 0x00 840Dh 0x00 840Eh 0x00 840Eh 0x00 840Fh 0x00 8410h 0x00 8411h 0x00 8412h 0x00 8413h 0x00 8414h 0x00 8415h 0x00 8416h 0x00 8417h MPU BYTE ADDRESS FFFB:0800 FFFB:0800 FFFB:0800 FFFB:0804 FFFB:0804 FFFB:0808 FFFB:0808 FFFB:0808 FFFB:080C FFFB:0810 FFFB:0810 FFFB:0814 FFFB:0814 FFFB:0818 FFFB:0818 FFFB:0818 FFFB:081C FFFB:081C FFFB:081C FFFB:0820 FFFB:0824 FFFB:0828 FFFB:0828 FFFB:082C FFFB:082C FFFB:0830 FFFB:0830 FFFB:0834 FFFB:0834 FFFB:0838 FFFB:0838 FFFB:083C FFFB:0840 FFFB:0844 FFFB:0848 FFFB:084C FFFB:0850 FFFB:0854 FFFB:0858 FFFB:085C UART2_MVR UART2_SYSC UART2_SYSS UART2_WER REGISTER NAME UART2_RHR UART2_THR UART2_DLL UART2_IER UART2_DLH UART2_IIR UART2_FCR UART2_EFR UART2_LCR UART2_MCR UART2_XON1 UART2_LSR UART2_XON2 UART2_MSR UART2_TCR UART2_XOFF UART2_SPR UART2_TLR UART2_XOFF2 UART2_MDR1 UART2_MDR2 UART2_SFLSR UART2_TXFLL UART2_RESUME UART2_TXFLH UART2_SFREGL UART2_RXFLL UART2_SFREGH UART2_RXFLH UART2_UASR UART2_BLR UART2_ACREG UART2_SCR UART2_SSR UART2_EBLR DESCRIPTION UART2 receive holding register UART2 transmit holding register UART2 divisor latch low register UART2 interrupt enable register UART2 divisor latch high register UART2 interrupt identification register UART2 FIFO control register UART2 enhanced feature register UART2 line control register UART2 modem control register UART2 XON1 register UART2 mode register UART2 XON2 register UART2 modem status register UART2 transmission control register UART2 XOFF1 register UART2 scratchpad register UART2 trigger level register UART2 XOFF2 register UART2 mode definition 1 register UART2 mode definition register 2 UART2 status FIFO line status register UART2 transmit frame length low UART2 resume register UART2 transmit frame length high UART2 status FIFO low register UART2 receive frame length low UART2 status FIFO high register UART2 receive frame length high UART2 autobauding status register UART2 BOF control register UART2 auxiliary control register UART2 supplementary control register UART2 supplementary status register UART2 BOF length register Reserved UART2 module version register UART2 system configuration register UART2 system status register UART2 wake-up enable register 8 8 8 8 R R/W R/W R/W - 00h 00h 7Fh ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W R/W R/W R/W R W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R W R W R W R W R R/W R/W R/W R R/W RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h 00h Undefined 0Fh 00h 00h 00h 00h 07h 00h 00h 00h 00h 00h Undefined 00h Undefined 00h 00h 40h 00h 00h 00h 00h
PRODUCT PREVIEW
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Functional Overview
Table 3-28. SPI1 Registers
BYTE ADDRESS FFFB:0C00 FFFB:0C04 - FFFB:0C0F FFFB:0C10 FFFB:0C14 FFFB:0C18 FFFB:0C1C FFFB:0C20 FFFB:0C24 FFFB:0C28 FFFB:0C2C FFFB:0C30 FFFB:0C34 FFFB:0C38 FFFB:0C3C SPI1_SET1 SPI1_SET2 SPI1_CTRL SPI1_DSR SPI1_TX SPI1_RX SPI1_TEST SPI1_SCR SPI1_SSR SPI1_ISR SPI1_IER REGISTER NAME SPI1_REV DESCRIPTION Module Version Register Reserved System Configuration Register System Status Register Interrupt Status Register Interrupt Enable Register Reserved Setup 1 Register Setup 2 Register Control Register Data Status Register Transmit Register Receive Register Test Register 32 32 32 32 32 32 32 R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0002h 0000 0000h 0000 0000h 0000 0000h 32 32 32 32 R/W R R/W R/W 0000 0020h 0000 0000h 0000 0000h 0000 0000h ACCESS WIDTH 32 ACCESS TYPE R RESET VALUE 0000 00XXh
Table 3-29. McBSP2 Registers
MPU BYTE ADDRESS FFFB:1000 FFFB:1002 FFFB:1004 FFFB:1006 FFFB:1008 FFFB:100A FFFB:100C FFFB:100E FFFB:1010 FFFB:1012 FFFB:1014 FFFB:1016 FFFB:1018 FFFB:101A FFFB:101C FFFB:101E FFFB:1020 FFFB:1022 FFFB:1024 FFFB:1026 FFFB:1028 FFFB:102A FFFB:102C FFFB:102E FFFB:1030 REGISTER NAME MCBSP2_DRR2 MCBSP2_DRR1 MCBSP2_DXR2 MCBSP2_DXR1 MCBSP2_SPCR2 MCBSP2_SPCR1 MCBSP2_RCR2 MCBSP2_RCR1 MCBSP2_XCR2 MCBSP2_XCR1 MCBSP2_SRGR2 MCBSP2_SRGR1 MCBSP2_MCR2 MCBSP2_MCR1 MCBSP2_RCERA MCBSP2_RCERB MCBSP2_XCERA MCBSP2_XCERB MCBSP2_PCR0 MCBSP2_RCERC MCBSP2_RCERD MCBSP2_XCERC MCBSP2_XCERD MCBSP2_RCERE MCBSP2_RCERF DESCRIPTION McBSP2 Data receive register 2 McBSP2 Data receive register 1 McBSP2 Data transmit register 2 McBSP2 Data transmit register 1 McBSP2 Serial port control register 2 McBSP2 Serial port control register 1 McBSP2 Receive control register 2 McBSP2 Receive control register 1 McBSP2 Transmit control register 2 McBSP2 Transmit control register 1 McBSP2 Sample rate generator register 2 McBSP2 Sample rate generator register 1 McBSP2 Multichannel register 2 McBSP2 Multichannel register 1 McBSP2 Receive channel enable register partition A McBSP2 Receive channel enable register partition B McBSP2 Transmit channel enable register partition A McBSP2 Transmit channel enable register partition B McBSP2 Pin control register 0 McBSP2 Receive channel enable register partition C McBSP2 Receive channel enable register partition D McBSP2 Transmit channel enable register partition C McBSP2 Transmit channel enable register partition D McBSP2 Receive channel enable register partition E McBSP2 Receive channel enable register partition F ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R//W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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PRODUCT PREVIEW
Functional Overview
Table 3-29. McBSP2 Registers (Continued)
MPU BYTE ADDRESS FFFB:1032 FFFB:1034 FFFB:1036 FFFB:1038 FFFB:103A FFFB:103C FFFB:103E REGISTER NAME MCBSP2_XCERE MCBSP2_XCERF MCBSP2_RCERG MCBSP2_RCERH MCBSP2_XCERG MCBSP2_XCERH MCBSP2_REV DESCRIPTION McBSP2 Transmit channel enable register partition E McBSP2 Transmit channel enable register partition F McBSP2 Receive channel enable register partition G McBSP2 Receive channel enable register partition H McBSP2 Transmit channel enable register partition G McBSP2 Transmit channel enable register partition H McBSP2 Version register ACCESS WIDTH 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0011h
Table 3-30. General-Purpose Timer1 Registers
DSP WORD ADDRESS 0x00 8A00h 0x00 8A02h 0x00 8A08h 0x00 8A0Ah 0x00 8A0Ch 0x00 8A0Eh 0x00 8A10h 0x00 8A12h 0x00 8A14h 0x00 8A16h 0x00 8A18h 0x00 8A1Ah 0x00 8A1Ch 0x00 8A1Eh 0x00 8A20h MPU BYTE ADDRESS FFFB:1400 FFFB:1404 FFFB:1410 FFFB:1414 FFFB:1418 FFFB:141C FFFB:1420 FFFB:1424 FFFB:1428 FFFB:142C FFFB:1430 FFFB:1434 FFFB:1438 FFFB:143C FFFB:1440 GPTMR1_TIOCP_CFG GPTMR1_TISTAT GPTMR1_TISR GPTMR1_TIER GPTMR1_TWER GPTMR1_TCLR GPTMR1_TCRR GPTMR1_TLDR GPTMR1_TTGR GPTMR1_TWPS GPTMR1_TMAR GPTMR1_TCAR GPTMR1_TSICR REGISTER NAME GPTMR1_TIDR DESCRIPTION GPTimer1 Identification Register Reserved GPTimer1 OCP Configuration Register GPTimer1 System Status Register GPTimer1 Status Register GPTimer1 Interrupt Enable Register GPTimer1 Wake Up Enable Register GPTimer1 Control Register GPTimer1 Counter Register GPTimer1 Load Register GPTimer1 Trigger Register GPTimer1 Write Posted Register GPTimer1 Match Register GPTimer1 Capture Register GPTimer1 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
PRODUCT PREVIEW
Table 3-31. General-Purpose Timer2 Registers
DSP WORD ADDRESS 0x00 8E00h 0x00 8E02h 0x00 8E08h 0x00 8E0Ah 0x00 8E0Ch 0x00 8E0Eh 0x00 8E10h 0x00 8E12h 0x00 8E14h 0x00 8E16h 0x00 8E18h 0x00 8E1Ah 0x00 8E1Ch MPU BYTE ADDRESS FFFB:1C00 FFFB:1C04 FFFB:1C10 FFFB:1C14 FFFB:1C18 FFFB:1C1C FFFB:1C20 FFFB:1C24 FFFB:1C28 FFFB:1C2C FFFB:1C30 FFFB:1C34 FFFB:1C38 GPTMR2_TIOCP_CFG GPTMR2_TISTAT GPTMR2_TISR GPTMR2_TIER GPTMR2_TWER GPTMR2_TCLR GPTMR2_TCRR GPTMR2_TLDR GPTMR2_TTGR GPTMR2_TWPS GPTMR2_TMAR REGISTER NAME GPTMR2_TIDR DESCRIPTION GPTimer2 Identification Register Reserved GPTimer2 OCP Configuration Register GPTimer2 System Status Register GPTimer2 Status Register GPTimer2 Interrupt Enable Register GPTimer2 Wake Up Enable Register GPTimer2 Control Register GPTimer2 Counter Register GPTimer2 Load Register GPTimer2 Trigger Register GPTimer2 Write Posted Register GPTimer2 Match Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
116
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Functional Overview
Table 3-31. General-Purpose Timer2 Registers (Continued)
DSP WORD ADDRESS 0x00 8E1Eh 0x00 8E20h MPU BYTE ADDRESS FFFB:1C3C FFFB:1C40 REGISTER NAME GPTMR2_TCAR GPTMR2_TSICR DESCRIPTION GPTimer2 Capture Register GPTimer2 Synchronization Interface Control Register ACCESS WIDTH 16/32 16/32 ACCESS TYPE R R/W RESET VALUE 0000 0000h 0000 0004h
Table 3-32. General-Purpose Timer3 Registers
DSP WORD ADDRESS 0x00 9200h 0x00 9202h 0x00 9208h 0x00 920Ah 0x00 920Ch 0x00 920Eh 0x00 9210h 0x00 9212h 0x00 9214h 0x00 9216h 0x00 9218h 0x00 921Ah 0x00 921Ch 0x00 921Eh 0x00 9220h MPU BYTE ADDRESS FFFB:2400 FFFB:2404 FFFB:2410 FFFB:2414 FFFB:2418 FFFB:241C FFFB:2420 FFFB:2424 FFFB:2428 FFFB:242C FFFB:2430 FFFB:2434 FFFB:2438 FFFB:243C FFFB:2440 GPTMR3_TIOCP_CFG GPTMR3_TISTAT GPTMR3_TISR GPTMR3_TIER GPTMR3_TWER GPTMR3_TCLR GPTMR3_TCRR GPTMR3_TLDR GPTMR3_TTGR GPTMR3_TWPS GPTMR3_TMAR GPTMR3_TCAR GPTMR3_TSICR REGISTER NAME GPTMR3_TIDR DESCRIPTION GPTimer3 Identification Register Reserved GPTimer3 OCP Configuration Register GPTimer3 System Status Register GPTimer3 Status Register GPTimer3 Interrupt Enable Register GPTimer3 Wake Up Enable Register GPTimer3 Control Register GPTimer3 Counter Register GPTimer3 Load Register GPTimer3 Trigger Register GPTimer3 Write Posted Register GPTimer3 Match Register GPTimer3 Capture Register GPTimer3 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h 0000 0000h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
Table 3-33. General-Purpose Timer4 Registers
DSP WORD ADDRESS 0x00 9600h 0x00 9602h 0x00 9608h 0x00 960Ah 0x00 960Ch 0x00 960Eh 0x00 9610h 0x00 9612h 0x00 9614h 0x00 9616h 0x00 9618h 0x00 961Ah 0x00 961Ch 0x00 961Eh 0x00 9620h MPU BYTE ADDRESS FFFB:2C00 FFFB:2C04 FFFB:2C10 FFFB:2C14 FFFB:2C18 FFFB:2C1C FFFB:2C20 FFFB:2C24 FFFB:2C28 FFFB:2C2C FFFB:2C30 FFFB:2C34 FFFB:2C38 FFFB:2C3C FFFB:2C40 GPTMR4_TIOCP_CFG GPTMR4_TISTAT GPTMR4_TISR GPTMR4_TIER GPTMR4_TWER GPTMR4_TCLR GPTMR4_TCRR GPTMR4_TLDR GPTMR4_TTGR GPTMR4_TWPS GPTMR4_TMAR GPTMR4_TCAR GPTMR4_TSICR REGISTER NAME GPTMR4_TIDR DESCRIPTION GPTimer4 Identification Register Reserved GPTimer4 OCP Configuration Register GPTimer4 System Status Register GPTimer4 Status Register GPTimer4 Interrupt Enable Register GPTimer4 Wake Up Enable Register GPTimer4 Control Register GPTimer4 Counter Register GPTimer4 Load Register GPTimer4 Trigger Register GPTimer4 Write Posted Register GPTimer4 Match Register GPTimer4 Capture Register GPTimer4 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
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PRODUCT PREVIEW
Functional Overview
Table 3-34. General-Purpose Timer5 Registers
DSP WORD ADDRESS 0x00 9A00h 0x00 9A02h 0x00 9A08h 0x00 9A0Ah 0x00 9A0Ch 0x00 9A0Eh 0x00 9A10h 0x00 9A12h 0x00 9A14h 0x00 9A16h 0x00 9A18h 0x00 9A1Ah 0x00 9A1Ch 0x00 9A1Eh 0x00 9A20h MPU BYTE ADDRESS FFFB:3400 FFFB:3404 FFFB:3410 FFFB:3414 FFFB:3418 FFFB:341C FFFB:3420 FFFB:3424 FFFB:3428 FFFB:342C FFFB:3430 FFFB:3434 FFFB:3438 FFFB:343C FFFB:3440 GPTMR5_TIOCP_CFG GPTMR5_TISTAT GPTMR5_TISR GPTMR5_TIER GPTMR5_TWER GPTMR5_TCLR GPTMR5_TCRR GPTMR5_TLDR GPTMR5_TTGR GPTMR5_TWPS GPTMR5_TMAR GPTMR5_TCAR GPTMR5_TSICR REGISTER NAME GPTMR5_TIDR DESCRIPTION GPTimer5 Identification Register Reserved GPTimer5 OCP Configuration Register GPTimer5 System Status Register GPTimer5 Status Register GPTimer5 Interrupt Enable Register GPTimer5 Wake Up Enable Register GPTimer5 Control Register GPTimer5 Counter Register GPTimer5 Load Register GPTimer5 Trigger Register GPTimer5 Write Posted Register GPTimer5 Match Register GPTimer5 Capture Register GPTimer5 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
PRODUCT PREVIEW
Table 3-35. I2C1 Registers
MPU BYTE ADDRESS FFFB:3800 FFFB:3804 FFFB:3808 FFFB:380C FFFB:3810 FFFB:3814 FFFB:3818 FFFB:381C FFFB:3820 FFFB:3824 FFFB:3828 FFFB:382C FFFB:3830 FFFB:3834 FFFB:3838 FFFB:383C I2C1_SYSS I2C1_BUF I2C1_CNT I2C1_DATA I2C1_SYSC I2C1_CON I2C1_OA I2C1_SA I2C1_PSC I2C1_SCLL I2C1_SCLH I2C1_SYSTEST REGISTER NAME I2C1_REV I2C1_IE I2C1_STAT DESCRIPTION I2C1 Module Version Register I2C1 Interrupt Enable Register I2C1 Status Register Reserved I2C1 System Status Register I2C1 Buffer Configuration Register I2C1 I2C1 Data Counter Register System Configuration Register I2C1 Data Access Register I2C1 Configuration Register I2C1 Own Address Register I2C1 Slave Address Register I2C1 Clock Prescaler Register I2C1 SCL Low Timer Register I2C1 SCL High Timer Register I2C1 System Test Register 16 16 16 16 16 16 16 16 16 16 16 16 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0000h 0000h 0000h 0000h 0000h 0000h 03FFh 0000h 0000h 0000h 0000h ACCESS WIDTH 16 16 16 ACCESS TYPE R/W R/W R RESET VALUE 0022h 0000h 0000h
118
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Functional Overview
Table 3-36. General-Purpose Timer6 Registers
DSP WORD ADDRESS 0x00 9E00h 0x00 9E02h 0x00 9E08h 0x00 9E0Ah 0x00 9E0Ch 0x00 9E0Eh 0x00 9E10h 0x00 9E12h 0x00 9E14h 0x00 9E16h 0x00 9E18h 0x00 9E1Ah 0x00 9E1Ch 0x00 9E1Eh 0x00 9E20h MPU BYTE ADDRESS FFFB:3C00 FFFB:3C04 FFFB:3C10 FFFB:3C14 FFFB:3C18 FFFB:3C1C FFFB:3C20 FFFB:3C24 FFFB:3C28 FFFB:3C2C FFFB:3C30 FFFB:3C34 FFFB:3C38 FFFB:3C3C FFFB:3C40 GPTMR6_TIOCP_CFG GPTMR6_TISTAT GPTMR6_TISR GPTMR6_TIER GPTMR6_TWER GPTMR6_TCLR GPTMR6_TCRR GPTMR6_TLDR GPTMR6_TTGR GPTMR6_TWPS GPTMR6_TMAR GPTMR6_TCAR GPTMR6_TSICR REGISTER NAME GPTMR6_TIDR DESCRIPTION GPTimer6 Identification Register Reserved GPTimer6 OCP Configuration Register GPTimer6 System Status Register GPTimer6 Status Register GPTimer6 Interrupt Enable Register GPTimer6 Wake Up Enable Register GPTimer6 Control Register GPTimer6 Counter Register GPTimer6 Load Register GPTimer6 Trigger Register GPTimer6 Write Posted Register GPTimer6 Match Register GPTimer6 Capture Register GPTimer6 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
Table 3-37. General-Purpose Timer7 Registers
DSP WORD ADDRESS 0x00 BA00h 0x00 BA02h 0x00 BA08h 0x00 BA0Ah 0x00 BA0Ch 0x00 BA0Eh 0x00 BA10h 0x00 BA12h 0x00 BA14h 0x00 BA16h 0x00 BA18h 0x00 BA1Ah 0x00 BA1Ch 0x00 BA1Eh 0x00 BA20h BYTE ADDRESS FFFB:7400 FFFB:7404 FFFB:7410 FFFB:7414 FFFB:7418 FFFB:741C FFFB:7420 FFFB:7424 FFFB:7428 FFFB:742C FFFB:7430 FFFB:7434 FFFB:7438 FFFB:743C FFFB:7440 GPTMR7_TIOCP_CFG GPTMR7_TISTAT GPTMR7_TISR GPTMR7_TIER GPTMR7_TWER GPTMR7_TCLR GPTMR7_TCRR GPTMR7_TLDR GPTMR7_TTGR GPTMR7_TWPS GPTMR7_TMAR GPTMR7_TCAR GPTMR7_TSICR REGISTER NAME GPTMR7_TIDR DESCRIPTION GPTimer7 Identification Register Reserved GPTimer7 OCP Configuration Register GPTimer7 System Status Register GPTimer7 Status Register GPTimer7 Interrupt Enable Register GPTimer7 Wake Up Enable Register GPTimer7 Control Register GPTimer7 Counter Register GPTimer7 Load Register GPTimer7 Trigger Register GPTimer7 Write Posted Register GPTimer7 Match Register GPTimer7 Capture Register GPTimer7 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
December 2003 - Revised March 2004
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PRODUCT PREVIEW
Functional Overview
Table 3-38. MMC/SDIO2 Registers
MPU BYTE ADDRESS FFFB:7C00 FFFB:7C04 FFFB:7C08 FFFB:7C0C FFFB:7C10 FFFB:7C14 FFFB:7C18 FFFB:7C1C FFFB:7C20 FFFB:7C24 FFFB:7C28 FFFB:7C2C FFFB:7C30 FFFB:7C34 FFFB:7C38 FFFB:7C3C FFFB:7C40 FFFB:7C44 FFFB:7C48 FFFB:7C4C FFFB:7C50 FFFB:7C54 FFFB:7C58 FFFB:7C5C FFFB:7C60 FFFB:7C64 FFFB:7C68 REGISTER NAME MMC2_CMD MMC2_ARGL MMC2_ARGH MMC2_CON MMC2_STAT MMC2_IE MMC2_CTO MMC2_DTO MMC2_DATA MMC2_BLEN MMC2_NBLK MMC2_BUF MMC2_SPI MMC2_SDIO MMC2_SYST MMC2_REV MMC2_RSP0 MMC2_RSP1 MMC2_RSP2 MMC2_RSP3 MMC2_RSP4 MMC2_RSP5 MMC2_RSP6 MMC2_RSP7 MMC2_IOSR MMC2_SYSC MMC2_SYSS DESCRIPTION MMC2 Command Register MMC2 Argument Register Low MMC2 Argument Register High MMC2 Module Configuration Register MMC2 Module Status Register MMC2 System Interrupt Enable Register MMC2 Command Time-Out Register MMC2 Data Read Time-Out Register MMC2 Data Access Register MMC2 Block Length Register MMC2 Numberf of Blocks Register MMC2 Buffer Configuration Register MMC2 SPI Configuration Register MMC2 SDIO Configuration Register MMC2 System Test Register MMC2 Module Revision Register MMC2 Command Response Register 0 MMC2 Command Response Register 1 MMC2 Command Response Register 2 MMC2 Command Response Register 3 MMC2 Command Response Register 4 MMC2 Command Response Register 5 MMC2 Command Response Register 6 MMC2 Command Response Register 7 MMC2 Command Response IOSR Register MMC2 System Control Register MMC2 System Status Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R/W R/W R RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h undefined 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
PRODUCT PREVIEW
Table 3-39. UART3 Registers
DSP WORD ADDRESS 0x00 CC00h 0x00 CC00h 0x00 CC00h 0x00 CC01h 0x00 CC01h 0x00 CC02h 0x00 CC02h 0x00 CC02h 0x00 CC03h 0x00 CC04h 0x00 CC04h 0x00 CC05h MPU BYTE ADDRESS FFFB:9800 FFFB:9800 FFFB:9800 FFFB:9804 FFFB:9804 FFFB:9808 FFFB:9808 FFFB:9808 FFFB:980C FFFB:9810 FFFB:9810 FFFB:9814 REGISTER NAME UART3_RHR UART3_THR UART3_DLL UART3_IER UART3_DLH UART3_IIR UART3_FCR UART3_EFR UART3_LCR UART3_MCR UART1_XON1 UART3_LSR DESCRIPTION UART3 receive holding register UART3 transmit holding register UART3 divisor latch low register UART3 interrupt enable register UART3 divisor latch high register UART3 interrupt identification register UART3 FIFO control register UART3 enhanced feature register UART3 line control register UART3 modem control register UART3 XON1 register UART3 mode register ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R W R/W R/W R/W R W R/W R/W R/W R/W R RESET VALUE Undefined Undefined 00h 00h 00h 01h 00h 00h 00h 00h 00h 60h
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SPRS231B
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Functional Overview
Table 3-39. UART3 Registers (Continued)
DSP WORD ADDRESS 0x00 CC05h 0x00 CC06h 0x00 CC06h 0x00 CC06h 0x00 CC07h 0x00 CC07h 0x00 CC07h 0x00 CC08h 0x00 CC09h 0x00 CC0Ah 0x00 CC0Ah 0x00 CC0Bh 0x00 CC0Bh 0x00 CC0Ch 0x00 CC0Ch 0x00 CC0Dh 0x00 CC0Dh 0x00 CC0Eh 0x00 CC0Eh 0x00 CC0Fh 0x00 CC10h 0x00 CC11h 0x00 CC12h 0x00 CC13h 0x00 CC14h 0x00 CC15h 0x00 CC16h 0x00 CC17h MPU BYTE ADDRESS FFFB:9814 FFFB:9818 FFFB:9818 FFFB:9818 FFFB:981C FFFB:981C FFFB:981C FFFB:9820 FFFB:9824 FFFB:9828 FFFB:9828 FFFB:982C FFFB:982C FFFB:9830 FFFB:9830 FFFB:9834 FFFB:9834 FFFB:9838 FFFB:9838 FFFB:983C FFFB:9840 FFFB:9844 FFFB:9848 FFFB:984C FFFB:9850 FFFB:9854 FFFB:9858 FFFB:985C UART3_MVR UART3_SYSC UART3_SYSS UART3_WER REGISTER NAME UART3_XON2 UART3_MSR UART3_TCR UART3_XOFF1 UART3_SPR UART3_TLR UART3_XOFF2 UART3_MDR1 UART3_MDR2 UART3_SFLSR UART3_TXFLL UART3_RESUME UART3_TXFLH UART3_SFREGL UART3_RXFLL UART3_SFREGH UART3_RXFLH UART3_UASR UART3_BLR UART3_ACREG UART3_SCR UART3_SSR UART3_EBLR DESCRIPTION UART3 XON2 register UART3 modem status register UART3 transmission control register UART3 XOFF1 register UART3 scratchpad register UART3 trigger level register UART3 XOFF2 register UART3 mode definition 1 register UART3 mode definition register 2 UART3 status FIFO line status register UART3 transmit frame length low UART3 resume register UART3 transmit frame length high UART3 status FIFO low register UART3 receive frame length low UART3 status FIFO high register UART3 receive frame length high UART3 autobauding status register UART3 BOF control register UART3 auxiliary control register UART3 supplementary control register UART3 supplementary status register UART3 BOF length register Reserved UART3 module version register UART3 system configuration register UART3 system status register UART3 wake-up enable register 8 8 8 8 R R/W R/W R/W - 00h 00h 7Fh ACCESS WIDTH 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 ACCESS TYPE R/W R R/W R/W R/W R/W R/W R/W R/W R W R W R W R W R R/W R/W R/W R R/W RESET VALUE 00h Undefined 0Fh 00h 00h 00h 00h 07h 00h 00h 00h 00h 00h 00h Undefined 00h 00h 40h 00h 00h 00h 00h Undefined
Table 3-40. MPU GPIO3 Registers
MPU BYTE ADDRESS FFFB:B400 FFFB:B410 FFFB:B414 FFFB:B418 FFFB:B41C FFFB:B420 FFFB:B424 FFFB:B428 FFFB:B42C FFFB:B430 FFFB:B434 REGISTER NAME GPIO3_REVISION GPIO3_SYSCONFIG GPIO3_SYSSTATUS GPIO3_IRQSTATUS1 GPIO3_IRQENABLE1 GPIO3_IRQSTATUS2 GPIO3_IRQENABLE2 GPIO3_WAKEUPENABLE GPIO3_DATAIN GPIO3_DATAOUT GPIO3_DIRECTION DESCRIPTION GPIO3 Revision Register GPIO3 System Configuration Register GPIO3 System Status Register GPIO3 Interrupt Status1 Register GPIO3 Interrupt Enable1 Register GPIO3 Interrupt Status2 Register GPIO3 Interrupt Enable2 Register GPIO3 Wake-up Enable Register GPIO3 Data Input Register GPIO3 Data Output Register GPIO3 Direction Control Register ACCESS WIDTH 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 ACCESS TYPE R R/W R R/W R/W R/W R/W R/W R R/W R/W RESET VALUE 0000 00xxh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 FFFFh
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PRODUCT PREVIEW
Functional Overview
Table 3-40. MPU GPIO3 Registers (Continued)
MPU BYTE ADDRESS FFFB:B438 FFFB:B43C FFFB:B49C FFFB:B4A4 FFFB:B4A8 FFFB:B4B0 FFFB:B4DC FFFB:B4E4 FFFB:B4E8 FFFB:B4F0 REGISTER NAME GPIO3_EDGE_CTRL1 GPIO3_EDGE_CTRL2 GPIO3_CLEAR_IRQENABLE1 GPIO3_CLEAR_IRQENABLE2 GPIO3_CLEAR_WAKEUPENA GPIO3_CLEAR_DATAOUT GPIO3_SET_IRQENABLE1 GPIO3_SET_IRQENABLE2 GPIO3_SET_WAKEUPENA GPIO3_SET_DATAOUT DESCRIPTION GPIO3 Edge Control 1 Register GPIO3 Edge Control 2 Register GPIO3 Clear Interrupt Enable1 Register GPIO3 Clear Interrupt Enable2 Register GPIO3 Clear Wake-up Enable Register GPIO3 Clear Data Output Register GPIO3 Set Interrupt Enable1 Register GPIO3 Set Interrupt Enable2 Register GPIO3 Set Wake-up Enable Register GPIO3 Set Data Output Register ACCESS WIDTH 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Table 3-41. MPU GPIO4 Registers
PRODUCT PREVIEW
MPU BYTE ADDRESS FFFB:BC00 FFFB:BC10 FFFB:BC14 FFFB:BC18 FFFB:BC1C FFFB:BC20 FFFB:BC24 FFFB:BC28 FFFB:BC2C FFFB:BC30 FFFB:BC34 FFFB:BC38 FFFB:BC3C FFFB:BC9C FFFB:BCA4 FFFB:BCA8 FFFB:BCB0 FFFB:BCDC FFFB:BCE4 FFFB:BCE8 FFFB:BCF0
REGISTER NAME GPIO4_REVISION GPIO4_SYSCONFIG GPIO4_SYSSTATUS GPIO4_IRQSTATUS1 GPIO4_IRQENABLE1 GPIO4_IRQSTATUS2 GPIO4_IRQENABLE2 GPIO4_WAKEUPENABLE GPIO4_DATAIN GPIO4_DATAOUT GPIO4_DIRECTION GPIO4_EDGE_CTRL1 GPIO4_EDGE_CTRL2 GPIO4_CLEAR_IRQENABLE1 GPIO4_CLEAR_IRQENABLE2 GPIO4_CLEAR_WAKEUPENA GPIO4_CLEAR_DATAOUT GPIO4_SET_IRQENABLE1 GPIO4_SET_IRQENABLE2 GPIO4_SET_WAKEUPENA GPIO4_SET_DATAOUT
DESCRIPTION GPIO4 Revision Register GPIO4 System Configuration Register GPIO4 System Status Register GPIO4 Interrupt Status1 Register GPIO4 Interrupt Enable1 Register GPIO4 Interrupt Status2 Register GPIO4 Interrupt Enable2 Register GPIO4 Wake-up Enable Register GPIO4 Data Input Register GPIO4 Data Output Register GPIO4 Direction Control Register GPIO4 Edge Control 1 Register GPIO4 Edge Control 2 Register GPIO4 Clear Interrupt Enable1 Register GPIO4 Clear Interrupt Enable2 Register GPIO4 Clear Wake-up Enable Register GPIO4 Clear Data Output Register GPIO4 Set Interrupt Enable1 Register GPIO4 Set Interrupt Enable2 Register GPIO4 Set Wake-up Enable Register GPIO4 Set Data Output Register
ACCESS WIDTH 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32
ACCESS TYPE R R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0000 00xxh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Table 3-42. 32-kHz Synchro Count Registers
MPU BYTE ADDRESS FFFB:D400 FFFB:D410 REGISTER NAME 32K_SYNC_CNT_REV 32K_SYNC_CNT_CR DESCRIPTION 32k Synchro Count CID Revision Register 32k Synchro Count Counter Register ACCESS WIDTH 32 32 ACCESS TYPE R R RESET VALUE 0000 0010h 0000 0003h
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SPRS231B
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Functional Overview
Table 3-43. General-Purpose Timer8 Registers
DSP WORD ADDRESS 0x00 C200h 0x00 C202h 0x00 C208h 0x00 C20Ah 0x00 C20Ch 0x00 C20Eh 0x00 C210h 0x00 C212h 0x00 C214h 0x00 C216h 0x00 C218h 0x00 C21Ah 0x00 C21Ch 0x00 C21Eh 0x00 C220h MPU BYTE ADDRESS FFFB:D400 FFFB:D404 FFFB:D410 FFFB:D414 FFFB:D418 FFFB:D41C FFFB:D420 FFFB:D424 FFFB:D428 FFFB:D42C FFFB:D430 FFFB:D434 FFFB:D438 FFFB:D43C FFFB:D440 GPTMR8_TIOCP_CFG GPTMR8_TISTAT GPTMR8_TISR GPTMR8_TIER GPTMR8_TWER GPTMR8_TCLR GPTMR8_TCRR GPTMR8_TLDR GPTMR8_TTGR GPTMR8_TWPS GPTMR8_TMAR GPTMR8_TCAR GPTMR8_TSICR REGISTER NAME GPTMR8_TIDR DESCRIPTION GPTimer8 Identification Register Reserved GPTimer8 OCP Configuration Register GPTimer8 System Status Register GPTimer8 Status Register GPTimer8 Interrupt Enable Register GPTimer8 Wake Up Enable Register GPTimer8 Control Register GPTimer8 Counter Register GPTimer8 Load Register GPTimer8 Trigger Register GPTimer8 Write Posted Register GPTimer8 Match Register GPTimer8 Capture Register GPTimer8 Synchronization Interface Control Register 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0004h ACCESS WIDTH 16/32 ACCESS TYPE R RESET VALUE 0000 0010h
Table 3-44. MPU GPIO1 Registers
MPU BYTE ADDRESS FFFB:E400 FFFB:E410 FFFB:E414 FFFB:E418 FFFB:E41C FFFB:E420 FFFB:E424 FFFB:E428 FFFB:E42C FFFB:E430 FFFB:E434 FFFB:E438 FFFB:E43C FFFB:E49C FFFB:E4A4 FFFB:E4A8 FFFB:E4B0 FFFB:E4DC FFFB:E4E4 FFFB:E4E8 FFFB:E4F0 REGISTER NAME GPIO1_REVISION GPIO1_SYSCONFIG GPIO1_SYSSTATUS GPIO1_IRQSTATUS1 GPIO1_IRQENABLE1 GPIO1_IRQSTATUS2 GPIO1_IRQENABLE2 GPIO1_WAKEUPENABLE GPIO1_DATAIN GPIO1_DATAOUT GPIO1_DIRECTION GPIO1_EDGE_CTRL1 GPIO1_EDGE_CTRL2 GPIO1_CLEAR_IRQENABLE1 GPIO1_CLEAR_IRQENABLE2 GPIO1_CLEAR_WAKEUPENA GPIO1_CLEAR_DATAOUT GPIO1_SET_IRQENABLE1 GPIO1_SET_IRQENABLE2 GPIO1_SET_WAKEUPENA GPIO1_SET_DATAOUT DESCRIPTION GPIO1 Revision Register GPIO1 System Configuration Register GPIO1 System Status Register GPIO1 Interrupt Status1 Register GPIO1 Interrupt Enable1 Register GPIO1 Interrupt Status2 Register GPIO1 Interrupt Enable2 Register GPIO1 Wake-up Enable Register GPIO1 Data Input Register GPIO1 Data Output Register GPIO1 Direction Control Register GPIO1 Edge Control 1 Register GPIO1 Edge Control 2 Register GPIO1 Clear Interrupt Enable1 Register GPIO1 Clear Interrupt Enable2 Register GPIO1 Clear Wake-up Enable Register GPIO1 Clear Data Output Register GPIO1 Set Interrupt Enable1 Register GPIO1 Set Interrupt Enable2 Register GPIO1 Set Wake-up Enable Register GPIO1 Set Data Output Register ACCESS WIDTH 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 ACCESS TYPE R R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 00xxh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
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Functional Overview
Table 3-45. MPU GPIO2 Registers
MPU BYTE ADDRESS FFFB:EC00 FFFB:EC10 FFFB:EC14 FFFB:EC18 FFFB:EC1C FFFB:EC20 FFFB:EC24 FFFB:EC28 FFFB:EC2C FFFB:EC30 FFFB:EC34 FFFB:EC38 FFFB:EC3C FFFB:EC9C FFFB:ECA4 FFFB:ECA8 FFFB:ECB0 FFFB:ECDC FFFB:ECE4 FFFB:ECE8 FFFB:ECF0 REGISTER NAME GPIO2_REVISION GPIO2_SYSCONFIG GPIO2_SYSSTATUS GPIO2_IRQSTATUS1 GPIO2_IRQENABLE1 GPIO2_IRQSTATUS2 GPIO2_IRQENABLE2 GPIO2_WAKEUPENABLE GPIO2_DATAIN GPIO2_DATAOUT GPIO2_DIRECTION GPIO2_EDGE_CTRL1 GPIO2_EDGE_CTRL2 GPIO2_CLEAR_IRQENABLE1 GPIO2_CLEAR_IRQENABLE2 GPIO2_CLEAR_WAKEUPENA GPIO2_CLEAR_DATAOUT GPIO2_SET_IRQENABLE1 GPIO2_SET_IRQENABLE2 GPIO2_SET_WAKEUPENA GPIO2_SET_DATAOUT DESCRIPTION GPIO2 Revision Register GPIO2 System Configuration Register GPIO2 System Status Register GPIO2 Interrupt Status1 Register GPIO2 Interrupt Enable1 Register GPIO2 Interrupt Status2 Register GPIO2 Interrupt Enable2 Register GPIO2 Wake-up Enable Register GPIO2 Data Input Register GPIO2 Data Output Register GPIO2 Direction Control Register GPIO2 Edge Control 1 Register GPIO2 Edge Control 2 Register GPIO2 Clear Interrupt Enable1 Register GPIO2 Clear Interrupt Enable2 Register GPIO2 Clear Wake-up Enable Register GPIO2 Clear Data Output Register GPIO2 Set Interrupt Enable1 Register GPIO2 Set Interrupt Enable2 Register GPIO2 Set Wake-up Enable Register GPIO2 Set Data Output Register ACCESS WIDTH 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 16/32 ACCESS TYPE R R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 00xxh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 FFFFh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
PRODUCT PREVIEW
Table 3-46. MPU/DSP Shared Mailbox Registers
DSP WORD ADDRESS 0x00 F800h 0x00 F802h 0x00 F804h 0x00 F806h 0x00 F808h 0x00 F80Ah 0x00 F80Ch 0x00 F80Eh 0x00 F810h 0x00 F812h 0x00 F814h 0x00 F816h MPU BYTE ADDRESS FFFC:F000 FFFC:F004 FFFC:F008 FFFC:F00C FFFC:F010 FFFC:F014 FFFC:F018 FFFC:F01C FFFC:F020 FFFC:F024 FFFC:F028 FFFC:F02C REGISTER NAME ARM2DSP1 ARM2DSP1B DSP2ARM1 DSP2ARM1B DSP2ARM2 DSP2ARM2B ARM2DSP1_FLAG DSP2ARM1_FLAG DSP2ARM2_FLAG ARM2DSP2 ARM2DSP2B ARM2DSP2_FLAG DESCRIPTION MPU to DSP 1 Data Register MPU to DSP 1 Command Register DSP to MPU 1 Data Register DSP to MPU 1 Command Register DSP to MPU 2 Data Register DSP to MPU 2 Command Register MPU to DSP 1 Flag Register DSP to MPU 1 Flag Register DSP to MPU 2 Flag Register MPU to DSP 2 Data Register MPU to DSP 2 Command Register MPU to DSP 2 Flag Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 MPU ACCESS TYPE R/W R/W R R R R R R R R/W R/W R DSP ACCESS TYPE R R R/W R/W R/W R/W R R R R R R RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h undef undef undef 0000h 0000h undef
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Functional Overview
3.2.2.4
* * * *
DSP Public Peripheral Registers (Accessible Via MPUI Port)
The MPU public peripheral registers include the following: McBSP1 Registers MCSI1 Registers MCSI2 Registers McBSP3 Registers
Table 3-47. McBSP1 Registers
DSP WORD ADDRESS 0x00 8C00h 0x00 8C01h 0x00 8C02h 0x00 8C03h 0x00 8C04h 0x00 8C05h 0x00 8C06h 0x00 8C07h 0x00 8C08h 0x00 8C09h 0x00 8C0Ah 0x00 8C0Bh 0x00 8C0Ch 0x00 8C0Dh 0x00 8C0Eh 0x00 8C10h 0x00 8C11h 0x00 8C12h 0x00 8C13h 0x00 8C14h 0x00 8C15h 0x00 8C16h 0x00 8C17h 0x00 8C18h 0x00 8C19h 0x00 8C1Ah MPU BYTE ADDRESS (VIA MPUI) E101:1800 E101:1802 E101:1804 E101:1806 E101:1808 E101:180A E101:180C E101:180E E101:1810 E101:1812 E101:1814 E101:1816 E101:1818 E101:181A E101:181C E101:181E E101:1820 E101:1822 E101:1824 E101:1826 E101:1828 E101:182A E101:182C E101:182E E101:1830 E101:1832 REGISTER NAME MCBSP1_DRR2 MCBSP1_DRR1 MCBSP1_DXR2 MCBSP1_DXR1 MCBSP1_SPCR2 MCBSP1_SPCR1 MCBSP1_RCR2 MCBSP1_RCR1 MCBSP1_XCR2 MCBSP1_XCR1 MCBSP1_SRGR2 MCBSP1_SRGR1 MCBSP1_MCR2 MCBSP1_MCR1 MCBSP1_RCERA MCBSP1_RCERB MCBSP1_XCERA MCBSP1_XCERB MCBSP1_PCR0 MCBSP1_RCERC MCBSP1_RCERD MCBSP1_XCERC MCBSP1_XCERD MCBSP1_RCERE MCBSP1_RCERF MCBSP1_XCERE DESCRIPTION McBSP1 Data receive register 2 McBSP1 Data receive register 1 McBSP1 Data transmit register 2 McBSP1 Data transmit register 1 McBSP1 Serial port control register 2 McBSP1 Serial port control register 1 McBSP1 Receive control register 2 McBSP1 Receive control register 1 McBSP1 Transmit control register 2 McBSP1 Transmit control register 1 McBSP1 Sample rate generator register 2 McBSP1 Sample rate generator register 1 McBSP1 Multichannel register 2 McBSP1 Multichannel register 1 McBSP1 Receive channel enable register partition A McBSP1 Receive channel enable register partition B McBSP1 Transmit channel enable register partition A McBSP1 Transmit channel enable register partition B McBSP1 Pin control register 0 McBSP1 Receive channel enable register partition C McBSP1 Receive channel enable register partition D McBSP1 Transmit channel enable register partition C McBSP1 Transmit channel enable register partition D McBSP1 Receive channel enable register partition E McBSP1 Receive channel enable register partition F McBSP1 Transmit channel enable register partition E ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R//W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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PRODUCT PREVIEW
Functional Overview
Table 3-47. McBSP1 Registers (Continued)
DSP WORD ADDRESS 0x00 8C1Bh 0x00 8C1Ch 0x00 8C1Dh 0x00 8C1Eh 0x00 8C1Fh 0x00 8C20h MPU BYTE ADDRESS (VIA MPUI) E101:1834 E101:1836 E101:1838 E101:183A E101:183C E101:183E REGISTER NAME DESCRIPTION McBSP1 Transmit channel enable register partition F McBSP1 Receive channel enable register partition G McBSP1 Receive channel enable register partition H McBSP1 Transmit channel enable register partition G McBSP1 Transmit channel enable register partition H McBSP1 Version register ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0011h
MCBSP1_XCERF MCBSP1_RCERG MCBSP1_RCERH MCBSP1_XCERG MCBSP1_XCERH MCBSP1_REV
Table 3-48. MCSI1 Registers
PRODUCT PREVIEW
DSP WORD ADDRESS 0x00 9400h 0x00 9401h 0x00 9402h 0x00 9403h 0x00 9404h 0x00 9405h 0x00 9406h 0x00 9407h- 0x00 941Fh 0x00 9420h 0x00 9421h 0x00 9422h 0x00 9423h 0x00 9424h 0x00 9425h 0x00 9426h 0x00 9427h 0x00 9428h 0x00 9429h 0x00 942Ah 0x00 942Bh 0x00 942Ch 0x00 942Dh 0x00 942Eh 0x00 942Fh 0x00 9430h 0x00 9431h 0x00 9432h
MPU BYTE ADDRESS (VIA MPUI) E101:2800 E101:2802 E101:2804 E101:2806 E101:2808 E101:280A E101:280C
REGISTER NAME MCSI1_CONTROL_REG MCSI1_MAIN_PARAMETERS_REG MCSI1_INTERRUPTS_REG MCSI1_CHANNEL_USED_REG MCSI1_OVER_CLOCK_REG MCSI1_CLOCK_FREQUENCY_ REG MCSI1_STATUS_REG Reserved
DESCRIPTION MCSI1 control register MCSI1 main parameters register MCSI1 interrupts register MCSI1 channel used register MCSI1 over-clock register MCSI1 clock frequency register MCSI1 status register
ACCESS WIDTH 16 16 16 16 16 16 16
ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W
RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h
E101:2840 E101:2842 E101:2844 E101:2846 E101:2848 E101:284A E101:284C E101:284E E101:2850 E101:2852 E101:2854 E101:2856 E101:2858 E101:285A E101:285C E101:285E E101:2860 E101:2862 E101:2864
MCSI1_TX0 MCSI1_TX1 MCSI1_TX2 MCSI1_TX3 MCSI1_TX4 MCSI1_TX5 MCSI1_TX6 MCSI1_TX7 MCSI1_TX8 MCSI1_TX9 MCSI1_TX10 MCSI1_TX11 MCSI1_TX12 MCSI1_TX13 MCSI1_TX14 MCSI1_TX15 MCSI1_RX0 MCSI1_RX1 MCSI1_RX2
MCSI1 transmit word register 0 MCSI1 transmit word register 1 MCSI1 transmit word register 2 MCSI1 transmit word register 3 MCSI1 transmit word register 4 MCSI1 transmit word register 5 MCSI1 transmit word register 6 MCSI1 transmit word register 7 MCSI1 transmit word register 8 MCSI1 transmit word register 9 MCSI1 transmit word register 10 MCSI1 transmit word register 11 MCSI1 transmit word register 12 MCSI1 transmit word register 13 MCSI1 transmit word register 14 MCSI1 transmit word register 15 MCSI1 receive word register 0 MCSI1 receive word register 1 MCSI1 receive word register 2
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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Functional Overview
Table 3-48. MCSI1 Registers (Continued)
DSP WORD ADDRESS 0x00 9433h 0x00 9434h 0x00 9435h 0x00 9436h 0x00 9437h 0x00 9438h 0x00 9439h 0x00 943Ah 0x00 943Bh 0x00 943Ch 0x00 943Dh 0x00 943Eh 0x00 943Fh MPU BYTE ADDRESS (VIA MPUI) E101:2866 E101:2868 E101:286A E101:286C E101:286E E101:2870 E101:2872 E101:2874 E101:2876 E101:2878 E101:287A E101:287C E101:287E REGISTER NAME MCSI1_RX3 MCSI1_RX4 MCSI1_RX5 MCSI1_RX6 MCSI1_RX7 MCSI1_RX8 MCSI1_RX9 MCSI1_RX10 MCSI1_RX11 MCSI1_RX12 MCSI1_RX13 MCSI1_RX14 MCSI1_RX15 DESCRIPTION MCSI1 receive word register 3 MCSI1 receive word register 4 MCSI1 receive word register 5 MCSI1 receive word register 6 MCSI1 receive word register 7 MCSI1 receive word register 8 MCSI1 receive word register 9 MCSI1 receive word register 10 MCSI1 receive word register 11 MCSI1 receive word register 12 MCSI1 receive word register 13 MCSI1 receive word register 14 MCSI1 receive word register 15 ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R R R R R R R R R R R R R RESET VALUE Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Table 3-49. MCSI2 Registers
DSP WORD ADDRESS 0x00 9000h 0x00 9001h 0x00 9002h 0x00 9003h 0x00 9004h 0x00 9005h 0x00 9006h 0x00 9007h - 0x00 901Fh 0x00 9020h 0x00 9021h 0x00 9022h 0x00 9023h 0x00 9024h 0x00 9025h 0x00 9026h 0x00 9027h 0x00 9028h 0x00 9029h 0x00 902Ah 0x00 902Bh 0x00 902Ch 0x00 902Dh 0x00 902Eh 0x00 902Fh E101:2040 E101:2042 E101:2044 E101:2046 E101:2048 E101:204A E101:204C E101:204E E101:2050 E101:2052 E101:2054 E101:2056 E101:2058 E101:205A E101:205C E101:205E MPU BYTE ADDRESS (VIA MPUI) E101:2000 E101:2002 E101:2004 E101:2006 E101:2008 E101:200A E101:200C REGISTER NAME MCSI2_CONTROL_REG MCSI2_MAIN_PARAMETERS_REG MCSI2_INTERRUPTS_REG MCSI2_CHANNEL_USED_REG MCSI2_OVER_CLOCK_REG MCSI2_CLOCK_FREQUENCY_ REG MCSI2_STATUS_REG Reserved MCSI2_TX0 MCSI2_TX1 MCSI2_TX2 MCSI2_TX3 MCSI2_TX4 MCSI2_TX5 MCSI2_TX6 MCSI2_TX7 MCSI2_TX8 MCSI2_TX9 MCSI2_TX10 MCSI2_TX11 MCSI2_TX12 MCSI2_TX13 MCSI2_TX14 MCSI2_TX15 MCSI2 transmit word register 0 MCSI2 transmit word register 1 MCSI2 transmit word register 2 MCSI2 transmit word register 3 MCSI2 transmit word register 4 MCSI2 transmit word register 5 MCSI2 transmit word register 6 MCSI2 transmit word register 7 MCSI2 transmit word register 8 MCSI2 transmit word register 9 MCSI2 transmit word register 10 MCSI2 transmit word register 11 MCSI2 transmit word register 12 MCSI2 transmit word register 13 MCSI2 transmit word register 14 MCSI2 transmit word register 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DESCRIPTION MCSI2 control register MCSI2 main parameters register MCSI2 interrupts register MCSI2 channel used register MCSI2 over-clock register MCSI2 clock frequency register MCSI2 status register ACCESS WIDTH 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Functional Overview
Table 3-49. MCSI2 Registers (Continued)
DSP WORD ADDRESS 0x00 9030h 0x00 9031h 0x00 9032h 0x00 9033h 0x00 9034h 0x00 9035h 0x00 9036h 0x00 9037h 0x00 9038h 0x00 9039h 0x00 903Ah 0x00 903Bh 0x00 903Ch MPU BYTE ADDRESS (VIA MPUI) E101:2060 E101:2062 E101:2064 E101:2066 E101:2068 E101:206A E101:206C E101:206E E101:2070 E101:2072 E101:2074 E101:2076 E101:2078 E101:207A E101:207C E101:207E REGISTER NAME MCSI2_RX0 MCSI2_RX1 MCSI2_RX2 MCSI2_RX3 MCSI2_RX4 MCSI2_RX5 MCSI2_RX6 MCSI2_RX7 MCSI2_RX8 MCSI2_RX9 MCSI2_RX10 MCSI2_RX11 MCSI2_RX12 MCSI2_RX13 MCSI2_RX14 MCSI2_RX15 DESCRIPTION MCSI2 receive word register 0 MCSI2 receive word register 1 MCSI2 receive word register 2 MCSI2 receive word register 3 MCSI2 receive word register 4 MCSI2 receive word register 5 MCSI2 receive word register 6 MCSI2 receive word register 7 MCSI2 receive word register 8 MCSI2 receive word register 9 MCSI2 receive word register 10 MCSI2 receive word register 11 MCSI2 receive word register 12 MCSI2 receive word register 13 MCSI2 receive word register 14 MCSI2 receive word register 15 ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R R R R R R R R R R R R R R R R RESET VALUE Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
PRODUCT PREVIEW
0x00 903Dh 0x00 903Eh 0x00 903Fh
Table 3-50. McBSP3 Registers
DSP WORD ADDRESS 0x00 B800h 0x00 B801h 0x00 B802h 0x00 B803h 0x00 B804h 0x00 B805h 0x00 B806h 0x00 B807h 0x00 B808h 0x00 B809h 0x00 B80Ah 0x00 B80Bh 0x00 B80Ch 0x00 B80Dh 0x00 B80Eh 0x00 B810h 0x00 B811h 0x00 B812h 0x00 B813h MPU BYTE ADDRESS (VIA MPUI) E101:7000 E101:7002 E101:7004 E101:7006 E101:7008 E101:700A E101:700C E101:700E E101:7010 E101:7012 E101:7014 E101:7016 E101:7018 E101:701A E101:701C E101:701E E101:7020 E101:7022 E101:7024 REGISTER NAME MCBSP3_DRR2 MCBSP3_DRR1 MCBSP3_DXR2 MCBSP3_DXR1 MCBSP3_SPCR2 MCBSP3_SPCR1 MCBSP3_RCR2 MCBSP3_RCR1 MCBSP3_XCR2 MCBSP3_XCR1 MCBSP3_SRGR2 MCBSP3_SRGR1 MCBSP3_MCR2 MCBSP3_MCR1 MCBSP3_RCERA MCBSP3_RCERB MCBSP3_XCERA MCBSP3_XCERB MCBSP3_PCR0 DESCRIPTION McBSP3 Data receive register 2 McBSP3 Data receive register 1 McBSP3 Data transmit register 2 McBSP3 Data transmit register 1 McBSP3 Serial port control register 2 McBSP3 Serial port control register 1 McBSP3 Receive control register 2 McBSP3 Receive control register 1 McBSP3 Transmit control register 2 McBSP3 Transmit control register 1 McBSP3 Sample rate generator register 2 McBSP3 Sample rate generator register 1 McBSP3 Multichannel register 2 McBSP3 Multichannel register 1 McBSP3 Receive channel enable register partition A McBSP3 Receive channel enable register partition B McBSP3 Transmit channel enable register partition A McBSP3 Transmit channel enable register partition B McBSP3 Pin control register 0 ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R//W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 2000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Functional Overview
Table 3-50. McBSP3 Registers (Continued)
DSP WORD ADDRESS 0x00 B814h 0x00 B815h 0x00 B816h 0x00 B817h 0x00 B818h 0x00 B819h 0x00 B81Ah 0x00 B81Bh 0x00 B81Ch 0x00 B81Dh 0x00 B81Eh 0x00 B81Fh 0x00 B820h MPU BYTE ADDRESS (VIA MPUI) E101:7026 E101:7028 E101:702A E101:702C E101:702E E101:7030 E101:7032 E101:7034 E101:7036 E101:7038 E101:703A E101:703C E101:703E REGISTER NAME DESCRIPTION McBSP3 Receive channel enable register partition C McBSP3 Receive channel enable register partition D McBSP3 Transmit channel enable register partition C McBSP3 Transmit channel enable register partition D McBSP3 Receive channel enable register partition E McBSP3 Receive channel enable register partition F McBSP3 Transmit channel enable register partition E McBSP3 Transmit channel enable register partition F McBSP3 Receive channel enable register partition G McBSP3 Receive channel enable register partition H McBSP3 Transmit channel enable register partition G McBSP3 Transmit channel enable register partition H McBSP3 Version register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0011h
MCBSP3_RCERC MCBSP3_RCERD MCBSP3_XCERC MCBSP3_XCERD MCBSP3_RCERE MCBSP3_RCERF MCBSP3_XCERE MCBSP3_XCERF MCBSP3_RCERG MCBSP3_RCERH MCBSP3_XCERG MCBSP3_XCERH MCBSP3_REV
3.2.2.5
* * * * * * * * * * * * *
MPU Configuration Registers
The MPU public peripheral registers include the following: MPU UART TIPB Bus Switch Registers Ultra Low-Power Device Peripheral Registers OMAP5912 Configuration Registers Device Die Identification Registers Production Identification Registers L3 OCP Initiator Registers MPU Interface (MPUI) Registers TIPB (Private) Bridge 1 Configuration Registers Traffic Controller Registers MPU Clock/Reset/Power Mode Control Registers DPLL1 Configuration Register DSP MMU Registers TIPB (Public) Bridge2 Configuration Registers
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PRODUCT PREVIEW
Functional Overview
Table 3-51. MPU UART TIPB Bus Switch Registers
BYTE ADDRESS FFFB:C800 FFFB:C820 FFFB:C840 FFFB:C890 FFFB:C8A0 FFFB:C8B0 FFFB:C8C0 FFFB:C8D0 FFFB:C8E0 FFFB:C8F0 FFFB:C900 FFFB:C910 FFFB:C930 FFFB:C940 FFFB:C960 REGISTER NAME UART1_SSW_CONF UART2_SSW_CONF UART3_SSW_CONF MCBSP2_SSW_CONF I2C_SSW_CONF SPI_SSW_CONF DUALMODETIMER1_SSW_CONF DUALMODETIMER2_SSW_CONF DUALMODETIMER3_SSW_CONF DUALMODETIMER4_SSW_CONF DUALMODETIMER5_SSW_CONF DUALMODETIMER6_SSW_CONF DUALMODETIMER7_SSW_CONF DUALMODETIMER8_SSW_CONF MMCSD2_SSW_CONF DESCRIPTION UART1 Peripheral Ownership Register UART2 Peripheral Ownership Register UART3 Peripheral Ownership Register McBSP2 Peirpheral Ownership Register I2C Peripheral Ownership Register SPI Peripheral Ownership Register Dual Mode Timer1 Ownership Register Dual Mode Timer2 Ownership Register Dual Mode Timer3 Ownership Register Dual Mode Timer4 Ownership Register Dual Mode Timer5 Ownership Register Dual Mode Timer6 Ownership Register Dual Mode Timer7 Ownership Register Dual Mode Timer8 Ownership Register MMCSD2 Ownership Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h 0000 0001h
PRODUCT PREVIEW
Table 3-52. Ultra Low-Power Device Peripheral Registers
BYTE ADDRESS FFFE:0800 FFFE:0804 FFFE:0808 FFFE:080C FFFE:0810 FFFE:0814 FFFE:0818 - FFFE:0820 FFFE:0824 FFFE:0828 - FFFE:082C FFFE:0830 FFFE:0834 FFFE:0838 FFFE:083C FFFE:0840 FFFE:0844 FFFE:0848 FFFE:084C FFFE:0850 LOCK_TIME_REG APLL_CTRL_REG POWER_CTRL_REG CLOCK_CTRL_REG SOFT_REQ_REG COUNTER_32_FIQ_REG DPLL_CTRL_REG STATUS_REQ_REG SETUP_ULPD1_REG REGISTER NAME COUNTER_32_LSB COUNTER_32_MSB COUNTER_HIGH_FREQ_LSB COUNTER_HIGH_FREQ_MSB GAUGING_CTRL_REG IT_STATUS_REG DESCRIPTION ULPD 32-kHz Counter Register LSB ULPD 32-kHz Counter Register MSB ULPD High-Frequency Counter LSB Register ULPD High-Frequency Counter MSB Register ULPD Gauging Control Register ULPD Interrupt Status Register Reserved ULPD Wakeup Time Setup Register Reserved ULPD Clock Control Register ULPD Soft Clock Request Register ULPD Modem Shutdown Delay Register ULPD USB DPLL Control Register ULPD Hardware Request Status Register Reserved ULPD APLL Lock Time Register ULPD APLL Control Register ULPD Power Control Register 16 16 16 R/W R/W R/W 0960h undef 0008h 16 16 16 16 16 R/W R/W R/W R/W R/W 0000h 0000h 0001h 2211h undef 16 R/W 03FFh ACCESS WIDTH 16 16 16 16 16 16 ACCESS TYPE R R R R R/W R RESET VALUE 0001h 0001h 0001h 0000h 0000h 0000h
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Functional Overview
Table 3-53. OMAP5912 Configuration Registers
BYTE ADDRESS FFFE:1000 FFFE:1004 FFFE:1008 FFFE:100C FFFE:1010 FFFE:1014 FFFE:1018 FFFE:101C FFFE:1020 FFFE:1024 FFFE:1028 FFFE:102C FFFE:1030 FFFE:1034 FFFE:1038 FFFE:1040 FFFE:1044 FFFE:1048 FFFE:104C FFFE:1050 FFFE:1058 FFFE:1060 FFFE:1064 FFFE:1068 FFFE:1080 FFFE:1090 FFFE:1094 FFFE:1098 FFFE:109C FFFE:10A0 FFFE:10AC FFFE:10B4 FFFE:10B8 FFFE:10B8 FFFE:10C0 FFFE:10C4 FFFE:10D0 FFFE:10D4 FFFE:10D8 FFFE:10DC FFFE:10EC FFFE:10F0 FFFE:10F4 REGISTER NAME FUNC_MUX_CTRL_0 FUNC_MUX_CTRL_1 FUNC_MUX_CTRL_2 COMP_MODE_CTRL_0 FUNC_MUX_CTRL_3 FUNC_MUX_CTRL_4 FUNC_MUX_CTRL_5 FUNC_MUX_CTRL_6 FUNC_MUX_CTRL_7 FUNC_MUX_CTRL_8 FUNC_MUX_CTRL_9 FUNC_MUX_CTRL_A FUNC_MUX_CTRL_B FUNC_MUX_CTRL_C FUNC_MUX_CTRL_D PULL_DWN_CTRL_0 PULL_DWN_CTRL_1 PULL_DWN_CTRL_2 PULL_DWN_CTRL_3 GATE_INH_CTRL_0 CONF_REV VOLTAGE_CTRL_0 USB_TRANSCEIVER_CTRL LDO_PWRDN_CTRL MOD_CONF_CTRL_0 FUNC_MUX_CTRL_E FUNC_MUX_CTRL_F FUNC_MUX_CTRL_10 FUNC_MUX_CTRL_11 FUNC_MUX_CTRL_12 PULL_DWN_CTRL_4 PU_PD_SEL_0 PU_PD_SEL_1 PU_PD_SEL_2 PU_PD_SEL_3 PU_PD_SEL_4 FUNC_MUX_DSP_DMA_A FUNC_MUX_DSP_DMA_B FUNC_MUX_DSP_DMA_C FUNC_MUX_DSP_DMA_D FUNC_MUX_ARM_DMA_A FUNC_MUX_ARM_DMA_B FUNC_MUX_ARM_DMA_C DESCRIPTION Functional Mux Control Register 0 Functional Mux Control Register 1 Functional Mux Control Register 2 I/O Multiplex Enable Register 0 Functional Mux Control Register 3 Functional Mux Control Register 4 Functional Mux Control Register 5 Functional Mux Control Register 6 Functional Mux Control Register 7 Functional Mux Control Register 8 Functional Mux Control Register 9 Functional Mux Control Register A Functional Mux Control Register B Functional Mux Control Register C Functional Mux Control Register D Pull Down Control Register 0 Pull Down Control Register 1 Pull Down Control Register 2 Pull Down Control Register 3 Gate Inhibit Control Register 0 Configuration Revision Voltage Control Register 0 USB Transceiver Control Register LDO Power Down Control Register Module Configuration Register 0 Function Mux Control Register E Function Mux Control Register F Function Mux Control Register 10 Function Mux Control Register 11 Function Mux Control Register 12 Pull Down Control Register 4 Pull Up Pull Down Slection Register 0 Pull Up Pull Down Slection Register 1 Pull Up Pull Down Slection Register 2 Pull Up Pull Down Slection Register 3 Pull Up Pull Down Slection Register 4 DSP DMA Functional Mux Register A DSP DMA Functional Mux Register B DSP DMA Functional Mux Register C DSP DMA Functional Mux Register D ARM DMA Functional Mux Register A ARM DMA Functional Mux Register B ARM DMA Functional Mux Register C ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0002h 0000 0000h 0000 0006h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h undef undef undef undef undef undef undef
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PRODUCT PREVIEW
0000 0000h
Functional Overview
Table 3-53. OMAP5912 Configuration Registers (Continued)
BYTE ADDRESS FFFE:10F8 FFFE:10FC FFFE:1100 FFFE:1104 FFFE:1110 FFFE:1120 FFFE:1130 FFFE:1140 FFFE:1150 REGISTER NAME FUNC_MUX_ARM_DMA_D FUNC_MUX_ARM_DMA_E FUNC_MUX_ARM_DMA_F FUNC_MUX_ARM_DMA_G MOD_CONF_CTRL_1 SECCTRL CONF_STATUS RESET_CTRL MOD_CONF_CTRL_2 DESCRIPTION ARM DMA Functional Mux Register D ARM DMA Functional Mux Register E ARM DMA Functional Mux Register F ARM DMA Functional Mux Register G Module Confguration Control Register 1 Secure Mode Control Register Confguration Status Register Reset Control Register Configuration Control Register 2 ACCESS WIDTH 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R R/W R/W RESET VALUE undef undef undef undef undef 0000 0D1Ah 0000 0000h 0000 007Fh 0000 0002h
Table 3-54. Device Die Identification Registers
BYTE ADDRESS REGISTER NAME DIE_ID_LSB DIE_ID_MSB DESCRIPTION Device Die Identification Register (LSB) Device Die Identification Register (MSB) ACCESS WIDTH 32 32 ACCESS TYPE R R RESET VALUE undef undef
PRODUCT PREVIEW
FFFE:1800 FFFE:1804
Table 3-55. Production Identification Registers
BYTE ADDRESS FFFE:2000 FFFE:2004 REGISTER NAME PROD_ID_REG0 PROD_ID_REG1 DESCRIPTION Production Identification Register0 Production Identification Register1 ACCESS WIDTH 32 32 ACCESS TYPE R R RESET VALUE undef undef
Table 3-56. L3 OCP Initiator Registers
BYTE ADDRESS FFFE:C320 FFFE:C324 FFFE:C328 FFFE:C330 FFFE:C334 FFFE:C338 FFFE:C32C REGISTER NAME ADDR_FAULT MCMD_FAULT S_INTERRUPT0 S_INTERRUPT1 PROTECT SECURE_MODE ABORT_TYPE DESCRIPTION Address Fault Register Master Command Fault Register Interrupt Sensitvity Register0 Interrupt Sensitvity Register1 Memory Protect Register Secure Mode Register Abort Type Register ACCESS WIDTH 32 32 32 32 32 32 32 ACCESS TYPE R R R/W R/W R/W R/W R RESET VALUE 0000 0000h 0000 0000h 0000 0003h 0000 0003h 0000 0000h 0000 007Fh 0000 0000h
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Functional Overview
Table 3-57. MPU Interface (MPUI) Registers
BYTE ADDRESS FFFE:C900 FFFE:C904 FFFE:C908 FFFE:C90C FFFE:C910 FFFE:C914 FFFE:C918 FFFE:C91C FFFE:C920 FFFE:C924 REGISTER NAME CTRL_REG DEBUG_ADDR DEBUG_DATA DEBUG_FLAG STATUS_REG DSP_STATUS_REG DSP_BOOT_CONFIG DSP_API_CONFIG DSP_MISC_CONFIG ENHANCED_CTL DESCRIPTION MPUI Control Register MPUI Debug Address Register MPUI Debug Data Register MPUI Debug Flag Register MPUI Status Register MPUI DSP Status Register MPUI Boot Configuration Register MPUI DSP AP Configuration Register MPUI Miscellaneous Configuration Register Enhanced Control Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R R R R R R/W R/W R/W R/W RESET VALUE 0003 FFFFh 00FF FFFFh FFFF FFFFh 0000 1800h 0000 1FFFh 0000 0000h 0000 0000h 0000 FFFFh 0000 0000h 0000 0000h
Table 3-58. TIPB (Private) Bridge 1 Configuration Registers
BYTE ADDRESS FFFE:CA00 FFFE:CA04 FFFE:CA08 FFFE:CA0C FFFE:CA10 FFFE:CA14 FFFE:CA18 FFFE:CA1C FFFE:CA20 REGISTER NAME TIPB_CNTL TIPB_BUS_ALLOC MPU_TIPB_CNTL ENHANCED_TIPB_CNTL ADDRESS_DBG DATA_DEBUG_LOW DATA_DEBUG_HIGH DEBUG_CNTR_SIG ACCESS_CNTL DESCRIPTION Private TIPB Control Register Private TIPB Bus Allocation Register Private MPU TIPB Control Register Private Enhanced TIPB Control Register Private Debug Address Register Private Debug Data LSB Register Private Debug Data MSB Register Private Debug Control Signals Register Private Access Control Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R R R R R/W RESET VALUE FF11h 0009h 0000h 000Fh FFFFh FFFFh FFFFh 00FCh 0001h
Table 3-59. Traffic Controller EMIFS Registers
BYTE ADDRESS FFFE:CC0C FFFE:CC10 FFFE:CC14 FFFE:CC18 FFFE:CC1C FFFE:CC28 FFFE:CC2C FFFE:CC30 FFFE:CC34 FFFE:CC38 FFFE:CC40 FFFE:CC44 FFFE:CC48 FFFE:CC4C FFFE:CC50 FFFE:CC54 EMIFS_CFG_DYN_WAIT EMIFS_ABORT_ADDR EMIFS_ABORT_TYPE EMIFS_ABORT_TIMEOUT EMIFS_ADV_CS0_CONFIG EMIFS_ADV_CS1_CONFIG REGISTER NAME EMIFS_CONFIG_REG EMIFS_CS0_CONFIG EMIFS_CS1_CONFIG EMIFS_CS2_CONFIG EMIFS_CS3_CONFIG EMIFS_TIMEOUT1 EMIFS_TIMEOUT2 EMIFS_TIMEOUT3 ENDIANISM DESCRIPTION EMIFS Configuration Register EMIFS nCS0 Configuration Register EMIFS nCS1 Configuration Register EMIFS nCS2 Configuration Register EMIFS nCS3 Configuration Register EMIFS Dynamic Priority Timeout 1 Register EMIFS Dynamic Priority Timeout 2 Register EMIFS Dynamic Priority Timeout 3 Register Endianism Register Reserved EMIFS Dynamic Wait-States Register EMIFS Abort Address Register EMIFS Abort Type Register EMIFS Abort Timeout Register Advanced EMIFS Chip Select Configuration Register nCS0 Advanced EMIFS Chip Select Configuration Register nCS1 32 32 32 32 32 32 R/W R R R/W R/W R/W 0000 0000h 0000 0000h 0000 0000h 0000 01FFh 0000 0000h 0000 0000h ACCESS WIDTH 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE undef undef undef undef undef 0000 0000h 0000 0000h 0000 0000h 0000 0000h
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Functional Overview
Table 3-59. Traffic Controller EMIFS Registers (Continued)
BYTE ADDRESS FFFE:CC58 FFFE:CC5C REGISTER NAME EMIFS_ADV_CS2_CONFIG EMIFS_ADV_CS3_CONFIG DESCRIPTION Advanced EMIFS Chip Select Configuration Register nCS2 Advanced EMIFS Chip Select Configuration Register nCS3 ACCESS WIDTH 32 32 ACCESS TYPE R/W R/W RESET VALUE 0000 0000h 0000 0000h
Table 3-60. Traffic Controller OCP-T1/OCP-T2 Registers
BYTE ADDRESS FFFE:CC00 FFFE:CCA0 FFFE:CCA4 FFFE:CCA8 FFFE:CCAC FFFE:CCB0 REGISTER NAME OCP_T1_PRIO OCP_T1_TIMEOUT1 OCP_T1_TIMEOUT2 OCP_T1_TIMEOUT3 OCP_T1_ABORT_TIMEOUT OCP_T1_ABORT_ADDR OCP_T1_ABORT_TYPE CONFIG_REG OCP_T2_PRIO OCP_T2_TIMEOUT1 OCP_T2_TIMEOUT2 OCP_T2_TIMEOUT3 OCP_T2_ABORT_TIMEOUT OCP_T2_ABORT_ADDR OCP_T2_ABORT_TYPE DESCRIPTION OCP-T1 LRU Priority Register OCP-T1 Dynamic Priority Time-out Register 1 OCP-T1 Dynamic Priority Time-out Register 2 OCP-T1 Dynamic Priority Time-out Register 3 OCP-T1 Abort Time-out Register OCP-T1 Abort Address Register OCP-T1 Abort Type Register OCP Target Configuration Register OCP-T2 LRU Priority Register OCP-T2 Dynamic Priority Time-out Register 1 OCP-T2 Dynamic Priority Time-out Register 2 OCP-T2 Dynamic Priority Time-out Register 3 OCP-T2 Abort Time-out Register OCP-T2 Abort Address Register OCP-T2 Abort Type Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R R RESET VALUE 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 01FFh 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 01FFh 0000 0000h 0000 0000h
PRODUCT PREVIEW
FFFE:CCB4 FFFE:CCB8 FFFE:CCD0 FFFE:CCD4 FFFE:CCD8 FFFE:CCDC FFFE:CCE0 FFFE:CCE4 FFFE:CCE8
Table 3-61. Traffic Controller OCPI Registers
BYTE ADDRESS FFFE:C320 FFFE:C324 FFFE:C328 FFFE:C32C FFFE:C330 FFFE:C334 FFFE:C338 REGISTER NAME OCP_ADDR_FAULT OCP_MCMD_FAULT OCP_SINT0 OCP_ABORT_TYPE OCP_SINT1 OCP_PROT OCP_SMOD DESCRIPTION OCPI Address Fault Register OCP Master Command Fault Register OCP Sinterrupt 0 Register OCP Abort Type Register OCP Sinterrupt 1 Register OCP Protection Register OCPI Secure Mode Register ACCESS WIDTH 32 32 32 32 32 32 32 ACCESS TYPE R R R/W R/W R/W R/W R/W RESET VALUE 0000 0000h 0000 0000h 0000 0003h 0000 0000h 0000 0003h 0000 0000h 0000 003Fh
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Functional Overview
Table 3-62. Traffic Controller EMIFF Registers
BYTE ADDRESS FFFE:CC08 FFFE:CC20 FFFE:CC24 FFFE:CC3C FFFE:CC64 FFFE:CC68 FFFE:CC70 FFFE:CC74 FFFE:CC78 FFFE:CC80 FFFE:CC84 FFFE:CC8C FFFE:CC90 FFFE:CC94 FFFE:CC98 FFFE:CC9C FFFE:CCC0 FFFE:CCC4 FFFE:CCC8 FFFE:CCCC FFFE:CCBC REGISTER NAME EMIFF_PRIO_REG EMIFF_SDRAM_CONFIG EMIFF_MRS EMIFF_SDRAM_CONFIG_2 DLL_WRT_CTL DLL_WRT_STAT EMIFF_MRS_NEW EMIFF_EMRS0 EMIFF_EMRS1 EMIFF_OP EMIFF_MCMD EMIFF_TIMEOUT1 EMIFF_TIMEOUT2 EMIFF_TIMEOUT3 EMIFF_ABORT_ADDR EMIFF_ABORT_TYPE DLL_URD_CTL DLL_URD_STAT EMIFF_EMRS2 DLL_LRD_CTL DLL_LRD_STAT DESCRIPTION EMIFF Priority Register EMIFF SDRAM Configuration Register EMIFF SDRAM MRS Register EMIFF SDRAM Configuration Register 2 DLL WRT Control Register (write byte) DLL WRT Status Register (read lower byte) EMIFF SDRAM MRS Register (duplicate) EMIFF SDRAM EMRS 0 Register EMIFF SDRAM EMRS 1 Register EMIFF SDRAM Operation Register EMIFF SDRAM Manual Command Register EMIFF Dynamic Arb. Priority Timeout 1 Register EMIFF Dynamic Arb. Priority Timeout 2 Register EMIFF Dynamic Arb. Priority Timeout 3 Register EMIFF Abort Address Register EMIFF Abort Type Register DLL URD Control Register (read upper byte) DLL URD Status Register (read upper byte) EMIFF SDRAM EMRS 2 Register DLL LRD Control Register (read lower byte) DLL LRD Status Register (read lower byte) ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R/W R/W R RESET VALUE 0000 0000h 0061 8800h 0000 0037h 0000 0003h 0000 0000h 0000 0000h 0000 0037h 0000 0000h 0000 0000h 0000 0004h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
Table 3-63. MPU Clock/Reset/Power Mode Control Registers
BYTE ADDRESS FFFE:CE00 FFFE:CE04 FFFE:CE08 FFFE:CE0C FFFE:CE10 FFFE:CE14 FFFE:CE18 FFFE:CE1C FFFE:CE20 FFFE:CE24 REGISTER NAME ARM_CKCTL ARM_IDLECT1 ARM_IDLECT2 ARM_EWUPCT ARM_RSTCT1 ARM_RSTCT2 ARM_SYSST ARM_CKOUT1 ARM_CKOUT2 ARM_IDLECT3 DESCRIPTION MPU Clock Control Register MPU Idle Control 1 Register MPU Idle Control 2 Register MPU External Wakeup Control Register MPU Reset Control 1 Register MPU Reset Control 2 Register MPU System Status Register MPU Clock Out Definition Register 1 MPU Clock Out Definition Register 2 MPU Idle Enable Control Register 3 ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 3000h 0400h 0100h 003Fh 0000h 0000h 0038h 0015h 0000h 0015h
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Functional Overview
Table 3-64. DPLL1 Configuration Register
BYTE ADDRESS FFFE:CF00 REGISTER NAME DPLL1_CTL_REG DESCRIPTION DPLL1 Control Register ACCESS WIDTH 32 ACCESS TYPE R/W RESET VALUE 0000 2002h
Table 3-65. DSP MMU Registers
BYTE ADDRESS FFFE:D200 FFFE:D204 FFFE:D208 FFFE:D20C FFFE:D210 FFFE:D214 FFFE:D218 FFFE:D21C FFFE:D220 FFFE:D224 FFFE:D228 FFFE:D22C FFFE:D230 FFFE:D234 FFFE:D238 FFFE:D23C FFFE:D240 FFFE:D244 FFFE:D248 FFFE:D24C FFFE:D250 REGISTER NAME DSP_MMU_PREFETCH_REG DSP_MMU_WALKING_ST_REG DSP_MMU_CNTL_REG DSP_MMU_FAULT_AD_H_REG DSP_MMU_FAULT_AD_L_REG DSP_MMU_F_ST_REG DSP_MMU_IT_ACK_REG DSP_MMU_TTB_H_REG DSP_MMU_TTB_L_REG DSP_MMU_LOCK_REG DSP_MMU_LD_TLB_REG DSP_MMU_CAM_H_REG DSP_MMU_CAM_L_REG DSP_MMU_RAM_H_REG DSP_MMU_RAM_L_REG DSP_MMU_GFLUSH_REG DSP_MMU_FLUSH_ENTRY_REG DSP_MMU_READ_CAM_H_REG DSP_MMU_READ_CAM_L_REG DSP_MMU_READ_RAM_H_REG DSP_MMU_READ_RAM_L_REG DESCRIPTION DSP MMU Prefetch Register DSP MMU Prefetch Status Register DSP MMU Control Register DSP MMU Fault Address Register MSB DSP MMU Fault Address Register LSB DSP MMU Fault Status Register DSP MMU IT Acknowledge Register DSP MMU TTB Register MSB DSP MMU TTB Register LSB DSP MMU Lock Counter Register DSP MMU Load Entry TLB Register DSP MMU CAM Entry Register MSB DSP MMU CAM Entry Register LSB DSP MMU RAM Entry Register MSB DSP MMU RAM Entry Register LSB DSP MMU Global Flush Register DSP MMU Individual Flush Register DSP MMU Read CAM Register MSB DSP MMU Read CAM Register LSB DSP MMU Read RAM Register MSB DSP MMU Read RAM Register LSB ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R R/W R R R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
PRODUCT PREVIEW
Table 3-66. TIPB (Public) Bridge 2 Configuration Registers
BYTE ADDRESS FFFE:D300 FFFE:D304 FFFE:D308 FFFE:D30C FFFE:D310 FFFE:D314 FFFE:D318 FFFE:D31C REGISTER NAME TIPB_CNTL TIPB_BUS_ALLOC MPU_TIPB_CNTL ENHANCED_TIPB_CNTL ADDRESS_DBG DATA_DEBUG_LOW DATA_DEBUG_HIGH DEBUG_CNTR_SIG DESCRIPTION Public TIPB Control Register Public TIPB Bus Allocation Register Public MPU TIPB Control Register Public Enhanced TIPB Control Register Public Debug Address Register Public Debug Data LSB Register Public Debug Data MSB Register Public Debug Control Signals Register ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R R R R RESET VALUE FF11h 0009h 0000h 0007h FFFFh FFFFh FFFFh 00F8h
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Functional Overview
3.3
DSP Memory Maps
The DSP supports a unified program/data memory map (program and data accesses are made to the same physical space); however, peripheral registers are located in a separate I/O space which is accessed via the DSP's port instructions.
3.3.1 DSP Global Memory Map
The DSP Subsystem contains 160K bytes of on-chip SRAM (64K bytes of DARAM and 96K bytes of SARAM). The MPU also has access to these memories via the MPUI (MPU Interface) port. The DSP also has access to the shared system SRAM (250K bytes) and both EMIF spaces (EMIFF and EMIFS) via the DSP Memory Management Unit (MMU) which is configured by the MPU. Table 3-67 shows the high-level program/data memory map for the DSP subsystem. DSP data accesses utilize 16-bit word addresses while DSP program fetches utilize byte addressing. Table 3-67. DSP Global Memory Map
BYTE ADDRESS RANGE 0x00 0000 - 0x00 FFFF 0x01 0000 - 0x02 7FFF 0x02 8000 - 0x04 FFFF 0x05 0000 - 0xFF 7FFF 0xFF 8000 - 0xFF FFFF
WORD ADDRESS RANGE 0x00 0000 - 0x00 7FFF 0x00 8000 - 0x01 3FFF 0x01 4000 - 0x02 7FFF 0x02 8000 - 0x7F BFFF 0x7F C000 - 0x7F FFFF
INTERNAL MEMORY DARAM 64K bytes SARAM 96K bytes Reserved
EXTERNAL MEMORY
Managed by DSP MMU PDROM (MPNMC = 0) Managed by DSP MMU (MPNMC =1)
This space could be external memory or internal shared system memory, depending on the DSP MMU configuration.
3.3.2 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h-00FFFFh and is composed of eight blocks of 8K bytes each (see Table 3-68). Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). Table 3-68. DARAM Blocks
DSP BYTE ADDRESS RANGE 0x00 0000 - 0x00 1FFF 0x00 2000 - 0x00 3FFF 0x00 4000 - 0x00 5FFF 0x00 6000 - 0x00 7FFF 0x00 8000 - 0x00 9FFF 0x00 A000 - 0x00 BFFF 0x00 C000 - 0x00 DFFF 0x00 E000 - 0x00 FFFF DSP WORD ADDRESS RANGE 0x00 0000 - 0x00 0FFF 0x00 1000 - 0x001FFF 0x00 2000 - 0x00 2FFF 0x00 3000 - 0x00 3FFF 0x00 4000 - 0x00 4FFF 0x00 5000 - 0x00 5FFF 0x00 6000 - 0x00 6FFF 0x00 7000 - 0x00 7FFF MEMORY BLOCK DARAM 0 DARAM 1 DARAM 2 DARAM 3 DARAM 4 DARAM 5 DARAM 6 DARAM 7
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Functional Overview
3.3.3 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h-027FFFh and is composed of 12 blocks of 8K bytes each (see Table 3-69). Each SARAM block can perform one access per cycle (one read or one write). Table 3-69. SARAM Blocks
DSP BYTE ADDRESS RANGE 0x01 0000 - 0x01 1FFF 0x01 2000 - 0x01 3FFF 0x01 4000 - 0x01 5FFF 0x01 6000 - 0x01 7FFF 0x01 8000 - 0x01 9FFF 0x01 A000 - 0x01 BFFF 0x01 C000 - 0x01 DFFF 0x01 E000 - 0x01 FFFF 0x02 0000 - 0x02 1FFF 0x02 2000 - 0x02 3FFF DSP WORD ADDRESS RANGE 0x00 8000 - 0x00 8FFF 0x00 9000 - 0x00 9FFF 0x00 A000 - 0x00 AFFF 0x00 B000 - 0x00 BFFF 0x00 C000 - 0x00 CFFF 0x00 D000 - 0x00 DFFF 0x00 E000 - 0x00 EFFF 0x00 F000 - 0x00 FFFF 0x01 0000 - 0x01 0FFF 0x01 1000 - 0x01 1FFF 0x01 2000 - 0x01 2FFF 0x01 3000 - 0x01 3FFF MEMORY BLOCK SARAM 0 SARAM 1 SARAM 2 SARAM 3 SARAM 4 SARAM 5 SARAM 6 SARAM 7 SARAM 8 SARAM 9 SARAM 10 SARAM 11
PRODUCT PREVIEW
0x02 4000 - 0x02 5FFF 0x02 6000 - 0x02 7FFF
3.3.4 DSP I/O Space Memory Map
The DSP I/O space is a separate address space from the data/program memory space. The I/O space is accessed via the DSP's port instructions. The DSP I/O space is accessed using 16-bit word addresses. Table 3-70 to Table 3-82 specify the DSP base addresses where each set of registers is accessed. All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing registers with the incorrect access width may cause unexpected results, including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt.
3.3.4.1
* * * * * * * *
DSP Private Peripheral Registers
The DSP Private Registers include the following: DSP DMA Controller Registers DSP Timer1 Registers DSP Timer2 Registers DSP Timer3 Registers DSP Watchdog Timer Registers DSP Level 2.0 Interrupt Handler Registers DSP Interrupt Interface Registers DSP Level 2.1 Interrupt Handler Registers
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Table 3-70. DSP DMA Controller Registers
DSP WORD ADDRESS 0x00 0C00h 0x00 0C01h 0x00 0C02h 0x00 0C03h 0x00 0C04h 0x00 0C05h 0x00 0C06h 0x00 0C07h 0x00 0C08h 0x00 0C09h 0x00 0C0Ah 0x00 0C0Bh 0x00 0C0Ch 0x00 0C0Dh 0x00 0C0Eh 0x00 0C0Fh 0x00 0C10h - 0x00 0C1Fh 0x00 0C20h 0x00 0C21h 0x00 0C22h 0x00 0C23h 0x00 0C24h 0x00 0C25h 0x00 0C26h 0x00 0C27h 0x00 0C28h 0x00 0C29h 0x00 0C2Ah 0x00 0C2Bh 0x00 0C2Ch 0x00 0C2Dh 0x00 0C2Eh 0x00 0C2Fh 0x00 0C30h - 0x00 0C3Fh 0x00 0C40h 0x00 0C41h 0x00 0C42h 0x00 0C43h 0x00 0C44h 0x00 0C45h 0x00 0C46h 0x00 0C47h DSP_DMA_CSDP2 DSP_DMA_CCR2 DSP_DMA_CICR2 DSP_DMA_CSR2 DSP_DMA_CSSA_L2 DSP_DMA_CSSA_U2 DSP_DMA_CDSA_L2 DSP_DMA_CDSA_U2 DSP_DMA_CSDP1 DSP_DMA_CCR1 DSP_DMA_CICR1 DSP_DMA_CSR1 DSP_DMA_CSSA_L1 DSP_DMA_CSSA_U1 DSP_DMA_CDSA_L1 DSP_DMA_CDSA_U1 DSP_DMA_CEN1 DSP_DMA_CFN1 DSP_DMA_CSFI1 DSP_DMA_CSEI1 DSP_DMA_CSAC1 DSP_DMA_CDAC1 DSP_DMA_CDFI1 DSP_DMA_CDEI1 REGISTER NAME DSP_DMA_CSDP0 DSP_DMA_CCR0 DSP_DMA_CICR0 DSP_DMA_CSR0 DSP_DMA_CSSA_L0 DSP_DMA_CSSA_U0 DSP_DMA_CDSA_L0 DSP_DMA_CDSA_U0 DSP_DMA_CEN0 DSP_DMA_CFN0 DSP_DMA_CSFI0 DSP_DMA_CSEI0 DSP_DMA_CSAC0 DSP_DMA_CDAC0 DSP_DMA_CDFI0 DSP_DMA_CDEI0 DESCRIPTION Channel 0 Source/Destination Parameters Register Channel 0 Control Register Channel 0 Interrupt Control Register Channel 0 Status Register Channel 0 Source Start Address Register LSB Channel 0 Source Start Address Register MSB Channel 0 Destination Start Address Register LSB Channel 0 Destination Start Address Register MSB Channel 0 Element Number Register Channel 0 Frame Number Register Channel 0 Frame Index Register Channel 0 Element Index Register Channel 0 Source Address Counter Register Channel 0 Destination Address Counter Register Channel 0 Destination Frame Index Channel 0 Destination Element Index Reserved Channel 1 Source/Destination Parameters Register Channel 1 Control Register Channel 1 Interrupt Control Register Channel 1 Status Register Channel 1 Source Start Address Register LSB Channel 1 Source Start Address Register MSB Channel 1 Destination Start Address Register LSB Channel 1 Destination Start Address Register MSB Channel 1 Element Number Register Channel 1 Frame Number Register Channel 1 Frame Index Register Channel 1 Element Index Register Channel 1 Source Address Counter Register Channel 1 Destination Address Counter Register Channel 1 Destination Frame Index Channel 1 Destination Element Index Reserved Channel 2 Source/Destination Parameters Register Channel 2 Control Register Channel 2 Interrupt Control Register Channel 2 Status Register Channel 2 Source Start Address Register LSB Channel 2 Source Start Address Register MSB Channel 2 Destination Start Address Register LSB Channel 2 Destination Start Address Register MSB 16 16 16 16 16 16 16 16 R/W R/W R/W R R/W R/W R/W R/W 0000h 0000h 0003h 0000h undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef
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Table 3-70. DSP DMA Controller Registers (Continued)
DSP WORD ADDRESS 0x00 0C48h 0x00 0C49h 0x00 0C4Ah 0x00 0C4Bh 0x00 0C4Ch 0x00 0C4Dh 0x00 0C4Eh 0x00 0C4Fh 0x00 0C50h - 0x00 0C5Fh 0x00 0C60h 0x00 0C61h 0x00 0C62h 0x00 0C63h DSP_DMA_CSDP3 DSP_DMA_CCR3 DSP_DMA_CICR3 DSP_DMA_CSR3 DSP_DMA_CSSA_L3 DSP_DMA_CSSA_U3 DSP_DMA_CDSA_L3 DSP_DMA_CDSA_U3 DSP_DMA_CEN3 DSP_DMA_CFN3 DSP_DMA_CSFI3 DSP_DMA_CSEI3 DSP_DMA_CSAC3 DSP_DMA_CDAC3 DSP_DMA_CDFI3 DSP_DMA_CDEI3 REGISTER NAME DSP_DMA_CEN2 DSP_DMA_CFN2 DSP_DMA_CSFI2 DSP_DMA_CSEI2 DSP_DMA_CSAC2 DSP_DMA_CDAC2 DSP_DMA_CDFI2 DSP_DMA_CDEI2 DESCRIPTION Channel 2 Element Number Register Channel 2 Frame Number Register Channel 2 Frame Index Register Channel 2 Element Index Register Channel 2 Source Address Counter Register Channel 2 Destination Address Counter Register Channel 2 Destination Frame Index Channel 2 Destination Element Index Reserved Channel 3 Source/Destination Parameters Register Channel 3 Control Register Channel 3 Interrupt Control Register Channel 3 Status Register Channel 3 Source Start Address Register LSB Channel 3 Source Start Address Register MSB Channel 3 Destination Start Address Register LSB Channel 3 Destination Start Address Register MSB Channel 3 Element Number Register Channel 3 Frame Number Register Channel 3 Frame Index Register Channel 3 Element Index Register Channel 3 Source Address Counter Register Channel 3 Destination Address Counter Register Channel 3 Destination Frame Index Channel 3 Destination Element Index Reserved DSP_DMA_CSDP4 DSP_DMA_CCR4 DSP_DMA_CICR4 DSP_DMA_CSR4 DSP_DMA_CSSA_L4 DSP_DMA_CSSA_U4 DSP_DMA_CDSA_L4 DSP_DMA_CDSA_U4 DSP_DMA_CEN4 DSP_DMA_CFN4 DSP_DMA_CSFI4 DSP_DMA_CSEI4 DSP_DMA_CSAC4 DSP_DMA_CDAC4 DSP_DMA_CDFI4 DSP_DMA_CDEI4 Channel 4 Source/Destination Parameters Register Channel 4 Control Register Channel 4 Interrupt Control Register Channel 4 Status Register Channel 4 Source Start Address Register LSB Channel 4 Source Start Address Register MSB Channel 4 Destination Start Address Register LSB Channel 4 Destination Start Address Register MSB Channel 4 Element Number Register Channel 4 Frame Number Register Channel 4 Frame Index Register Channel 4 Element Index Register Channel 4 Source Address Counter Register Channel 4 Destination Address Counter Register Channel 4 Destination Frame Index Channel 4 Destination Element Index 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE undef undef undef undef undef undef undef undef
PRODUCT PREVIEW
0x00 0C64h 0x00 0C65h 0x00 0C66h 0x00 0C67h 0x00 0C68h 0x00 0C69h 0x00 0C6Ah 0x00 0C6Bh 0x00 0C6Ch 0x00 0C6Dh 0x00 0C6Eh 0x00 0C6Fh 0x00 0C70h - 0x00 0C7Fh 0x00 0C80h 0x00 0C81h 0x00 0C82h 0x00 0C83h 0x00 0C84h 0x00 0C85h 0x00 0C86h 0x00 0C87h 0x00 0C88h 0x00 0C89h 0x00 0C8Ah 0x00 0C8Bh 0x00 0C8Ch 0x00 0C8Dh 0x00 0C8Eh 0x00 0C8Fh
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Table 3-70. DSP DMA Controller Registers (Continued)
DSP WORD ADDRESS 0x00 0C90h - 0x00 0C9Fh 0x00 0CA0h 0x00 0CA1h 0x00 0CA2h 0x00 0CA3h 0x00 0CA4h 0x00 0CA5h 0x00 0CA6h 0x00 0CA7h 0x00 0CA8h 0x00 0CA9h 0x00 0CAAh 0x00 0CABh 0x00 0CACh 0x00 0CADh 0x00 0CAEh 0x00 0CAFh 0x00 0CB0h - 0x00 0DFFh 0x00 0E00h 0x00 0E01h 0x00 0E02h DSP_DMA_GCR DSP_DMA_GTCR DSP_DMA_GSCR DSP_DMA_CSDP5 DSP_DMA_CCR5 DSP_DMA_CICR5 DSP_DMA_CSR5 DSP_DMA_CSSA_L5 DSP_DMA_CSSA_U5 DSP_DMA_CDSA_L5 DSP_DMA_CDSA_U5 DSP_DMA_CEN5 DSP_DMA_CFN5 DSP_DMA_CSFI5 DSP_DMA_CSEI5 DSP_DMA_CSAC5 DSP_DMA_CDAC5 DSP_DMA_CDFI5 DSP_DMA_CDEI5 REGISTER NAME Reserved Channel 5 Source/Destination Parameters Register Channel 5 Control Register Channel 5 Interrupt Control Register Channel 5 Status Register Channel 5 Source Start Address Register LSB Channel 5 Source Start Address Register MSB Channel 5 Destination Start Address Register LSB Channel 5 Destination Start Address Register MSB Channel 5 Element Number Register Channel 5 Frame Number Register Channel 5 Frame Index Register Channel 5 Element Index Register Channel 5 Source Address Counter Register Channel 5 Destination Address Counter Register Channel 5 Destination Frame Index Channel 5 Destination Element Index Reserved Global Control Register Global Timeout Control Register Global Software Incompatible Control Register 16 16 16 R/W R/W R/W 0008h 0000h 0000h 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 RW R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000h 0000h 0003h 0000h undef undef undef undef undef undef undef undef undef undef undef undef DESCRIPTION ACCESS WIDTH ACCESS TYPE RESET VALUE
Table 3-71. DSP Timer1 Registers
DSP WORD ADDRESS 0x00 2800h 0x00 2802h 0x00 2803h 0x00 2804h 0x00 2805h REGISTER NAME DSP_TMR1_CNTL DSP_TMR1_LOAD_LO DSP_TMR1_LOAD_HI DSP_TMR1_READ_LO DSP_TMR1_READ_HI DESCRIPTION DSP Timer1 Control Register DSP Timer1 Load Register Low DSP Timer1 Load Register High DSP Timer1 Read Register Low DSP Timer1 Read Register High ACCESS WIDTH 16 16 16 16 16 ACCESS TYPE R/W W W R R RESET VALUE 0000h undef undef undef undef
Table 3-72. DSP Timer2 Registers
DSP WORD ADDRESS 0x00 2C00h 0x00 2C02h 0x00 2C03h 0x00 2C04h 0x00 2C05h REGISTER NAME DSP_TMR2_CNTL DSP_TMR2_LOAD_LO DSP_TMR2_LOAD_HI DSP_TMR2_READ_LO DSP_TMR2_READ_HI DESCRIPTION DSP Timer2 Control Register DSP Timer2 Load Register Low DSP Timer2 Load Register High DSP Timer2 Read Register Low DSP Timer2 Read Register High ACCESS WIDTH 16 16 16 16 16 ACCESS TYPE R/W W W R R RESET VALUE 0000h undef undef undef undef
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Table 3-73. DSP Timer3 Registers
DSP WORD ADDRESS 0x00 3000h 0x00 3002h 0x00 3003h 0x00 3004h 0x00 3005h REGISTER NAME DSP_TMR3_CNTL DSP_TMR3_LOAD_LO DSP_TMR3_LOAD_HI DSP_TMR3_READ_LO DSP_TMR3_READ_HI DESCRIPTION DSP Timer3 Control Register DSP Timer3 Load Register Low DSP Timer3 Load Register High DSP Timer3 Read Register Low DSP Timer3 Read Register High ACCESS WIDTH 16 16 16 16 16 ACCESS TYPE R/W W W R R RESET VALUE 0000h undef undef undef undef
Table 3-74. DSP Watchdog Timer Registers
DSP WORD ADDRESS 0x00 3400h 0x00 3402h 0x00 3402h 0x00 3404h REGISTER NAME DSP_WD_CNTL_TIMER DSP_WD_LOAD_TIMER DSP_WD_READ_TIMER DSP_WD_TIMER_MODE DESCRIPTION DSP Watchdog Control Timer DSP Watchdog Load Timer DSP Watchdog Read Timer DSP Watchdog Timer Mode ACCESS WIDTH 16 16 16 16 ACCESS TYPE R/W W R R/W RESET VALUE 0E02h FFFFh FFFFh 8000h
PRODUCT PREVIEW
Table 3-75. DSP Level 2.0 Interrupt Handler Registers
DSP WORD ADDRESS TBD TBD REGISTER NAME TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
Table 3-76. DSP Interrupt Interface Registers
DSP WORD ADDRESS 0x00 3800h 0x00 3801h 0x00 3800h 0x00 3801h REGISTER NAME ET_LS_CTRL_HI ET_LS_CTRL_LO RST_LVL_HI RST_LVL_LO DESCRIPTION Edge Triggered/Level Sensitive Control Register High Edge Triggered/Level Sensitive Control Register Low Reset Level Control Register High Reset Level Control Register Low ACCESS WIDTH 16 16 16 16 ACCESS TYPE R/W R/W R/W R/W RESET VALUE 007Fh FFFFh 0000h 0000h
Table 3-77. DSP Level 2.1 Interrupt Handler Registers
DSP WORD ADDRESS 0x00 4C00h 0x00 4C02h 0x00 4C04h 0x00 4C06h 0x00 4C08h 0x00 4C0Ah 0x00 4C0Ch 0x00 4C0Eh 0x00 4C10h 0x00 4C12h 0x00 4C14h 0x00 4C16h 0x00 4C18h 0x00 4C1Ah REGISTER NAME DSP_L21_ITR DSP_L21_MIR DSP_L21_SIR_IRQ_CODE DSP_L21_SIR_FIQ_CODE DSP_L21_CONTROL_REG DSP_L21_ISR DSP_L21_ILR0 DSP_L21_ILR1 DSP_L21_ILR2 DSP_L21_ILR3 DSP_L21_ILR4 DSP_L21_ILR5 DSP_L21_ILR6 DSP_L21_ILR7 DESCRIPTION Interrupt Register Mask Interrupt Register IRQ Interrupt Encoded Source Register FIQ Interrupt Encoded Source Register Interrupt Control Register Software Interrupt Set Register Interrupt 0 Priority Level Register Interrupt 1 Priority Level Register Interrupt 2 Priority Level Register Interrupt 3 Priority Level Register Interrupt 4 Priority Level Register Interrupt 5 Priority Level Register Interrupt 6 Priority Level Register Interrupt 7 Priority Level Register ACCESS WIDTH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ACCESS TYPE R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000h FFFFh 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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Table 3-77. DSP Level 2.1 Interrupt Handler Registers (Continued)
DSP WORD ADDRESS 0x00 4C1Ch 0x00 4C1Eh 0x00 4C20h 0x00 4C22h 0x00 4C24h 0x00 4C26h 0x00 4C28h 0x00 4C2Ah REGISTER NAME DSP_L21_ILR8 DSP_L21_ILR9 DSP_L21_ILR10 DSP_L21_ILR11 DSP_L21_ILR12 DSP_L21_ILR13 DSP_L21_ILR14 DSP_L21_ILR15 DESCRIPTION Interrupt 8 Priority Level Register Interrupt 9 Priority Level Register Interrupt 10 Priority Level Register Interrupt 11 Priority Level Register Interrupt 12 Priority Level Register Interrupt 13 Priority Level Register Interrupt 14 Priority Level Register Interrupt 15 Priority Level Register ACCESS WIDTH 16 16 16 16 16 16 16 16 ACCESS RESET VALUE TYPE R/W R/W R/W R/W RW R/W R/W R/W 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
3.3.4.2
* * * * *
DSP Configuration Registers
DSP TIPB Bridge Configuration Registers DSP I-CACHE Registers DSP Clock Mode Registers DSP TIPB Bus Switch Registers
The DSP Private Registers include the following: DSP EMIF Configuration Registers
Table 3-78. DSP TIPB Bridge Configuration Registers
DSP WORD ADDRESS 0x00 0000 0x00 0002 0x00 0004 0x00 0006 0x00 0008 0x00 000E 0x00 0010 0x00 0012 0x00 0014 0x00 0016 0x00 0018 0x00 001A 0x00 0040 0x00 0042 0x00 0044 0x00 0046 0x00 0048 0x00 004A 0x00 004C 0x00 004E 0x00 0060 REGISTER NAME DSP_ID DSP_MODE DSP_FRAME_SIZE DSP_RXSTATE DSP_BUFSTATE DSP_BREAK DSP_ERROR DSP_ERRORACK DSP_CHANNELS DSP_OVERRUN DSP_OVERRUNACK DSP_TIMEOUT DSP_BUFFER_CH0 DSP_BUFFER_CH1 DSP_BUFFER_CH2 DSP_BUFFER_CH3 DSP_BUFFER_CH4 DSP_BUFFER_CH5 DSP_BUFFER_CH6 DSP_BUFFER_CH7 DSP_SWAPBUFFER_CH0 DESCRIPTION Identification Register Mode Register Frame Size Register Receive State Register Receive Buffer State Register Break Detection State Register Error Detection State Register Error Acknowledge Register Channels Register Overrun Register Overrun Acknowledge Register Timeout Period Register Reception Buffer Channel 0 Register Reception Buffer Channel 1 Register Reception Buffer Channel 2 Register Reception Buffer Channel 3 Register Reception Buffer Channel 4 Register Reception Buffer Channel 5 Register Reception Buffer Channel 6 Register Reception Buffer Channel 7 Register Byte Swapping Receive Buffer Channel 0 Register ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 5555 5555h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
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Table 3-78. DSP TIPB Bridge Configuration Registers (Continued)
DSP WORD ADDRESS 0x00 0062 0x00 0064 0x00 0066 0x00 0068 0x00 006A 0x00 006C 0x00 006E REGISTER NAME DSP_SWAPBUFFER_CH1 DSP_SWAPBUFFER_CH2 DSP_SWAPBUFFER_CH3 DSP_SWAPBUFFER_CH4 DSP_SWAPBUFFER_CH5 DSP_SWAPBUFFER_CH6 DSP_SWAPBUFFER_CH7 DESCRIPTION Byte Swapping Receive Buffer Channel 1 Register Byte Swapping Receive Buffer Channel 2 Register Byte Swapping Receive Buffer Channel 3 Register Byte Swapping Receive Buffer Channel 4 Register Byte Swapping Receive Buffer Channel 5 Register Byte Swapping Receive Buffer Channel 6 Register Byte Swapping Receive Buffer Channel 7 Register ACCESS WIDTH 32 32 32 32 32 32 32 ACCESS RESET VALUE TYPE R/W R/W R/W R/W R/W R/W R/W 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h
PRODUCT PREVIEW
Table 3-79. DSP EMIF Configuration Registers
DSP WORD ADDRESS TBD TBD REGISTER NAME TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
Table 3-80. DSP I-Cache Registers
DSP WORD ADDRESS TBD TBD REGISTER NAME TBD DESCRIPTION ACCESS WIDTH TBD ACCESS TYPE TBD RESET VALUE TBD
Table 3-81. DSP Clock Mode Registers
DSP WORD ADDRESS 0x00 4000 0x00 4002 0x00 4004 0x00 4006 0x00 4008 0x00 400A 0x00 400C DSP_RSTCT2 DSP_SYSST REGISTER NAME DSP_CKTL DSP_IDLCT1 DSP_IDLCT2 DESCRIPTION DSP Clock Control Register DSP Idle Control 1 Register DSP Idle Control 2Register Reserved Reserved DSP Reset Control 2 Register DSP System Information Register 16 16 R/W R/W 0000h 0000h ACCESS WIDTH 16 16 16 ACCESS TYPE R/W R/W R/W RESET VALUE 0190h 0040h 0000h
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Table 3-82. DSP TIPB Bus Switch Registers
DSP WORD ADDRESS 0x00 E400 0x00 E410 0x00 E420 0x00 E448 0x00 E450 0x00 E458 0x00 E460 0x00 E468 0x00 E470 0x00 E478 0x00 E480 0x00 E488 0x00 E498 0x00 E4A0 0x00 E4A8 0x00 E4B0 DSP_MMCSD2_SSW_CONF REGISTER NAME DSP_UART1_SSW_CONF DSP_UART2_SSW_CONF DSP_UART3_SSW_CONF DSP_MCBSP2_SSW_CONF DSP_I2C_SSW_CONF DSP_SPI_SSW_CONF DSP_GPTIMER1_SSW_CONF DSP_GPTIMER2_SSW_CONF DSP_GPTIMER3_SSW_CONF DSP_GPTIMER4_SSW_CONF DSP_GPTIMER5_SSW_CONF DSP_GPTIMER6_SSW_CONF DSP_GPTIMER7_SSW_CONF DSP_GPTIMER8_SSW_CONF DESCRIPTION UART1 Peripheral Ownership Register UART2 Peripheral Ownership Register UART3 Peripheral Ownership Register MCBSP2 Peripheral Ownership Register I2C Peripheral Ownership Register SPI Peripheral Ownership Register GPTIMER1 Peripheral Ownership Register GPTIMER2 Peripheral Ownership Register GPTIMER3 Peripheral Ownership Register GPTIMER4 Peripheral Ownership Register GPTIMER5 Peripheral Ownership Register GPTIMER6 Peripheral Ownership Register GPTIMER7 Peripheral Ownership Register GPTIMER8 Peripheral Ownership Register Reserved MMC/SDIO 2 Peripheral Ownership Register 32 R/W 0000 00001h ACCESS WIDTH 32 32 32 32 32 32 32 32 32 32 32 32 32 32 ACCESS TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h 0000 00001h
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Functional Overview
3.4
DSP External Memory (Managed by MMU)
When the DSP MMU is off, the 24 address lines are directly copied to the traffic controller without any modification. There is no virtual-to-physical address translation. All the addresses between 0x05 0000 and 0x00FF 8000 (0x00FF FFFF if DSP bit MP/MC = 1) are redirected to the first sector of Flash (CS0) in the shared memory space (shared by MPU and DSP). See Figure 3-2.
Byte Address 0x00 0000 Internal RAM 0x05 0000 FLASH CS0 0x0400 0000 FLASH CS1 0x0800 0000 FLASH CS2 0x0C00 0000 Byte Address 0x0000 0000
DSP Memory
Shared Memory
PRODUCT PREVIEW
FLASH CS3 0xFF 8000 ROM 0xFF FFFF SDRAM 0x17FF FFFF Reserved 0x2000 0000 Internal SRAM (Frame Buffer) 0x2003 E7FF 0x1000 0000
Figure 3-2. DSP MMU Off
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When the DSP MMU is on, the 24 address lines (virtual address) are relocated within a physical 32-bit address by the DSP MMU. The DSP MMU is controlled by the MPU. See Figure 3-3.
Byte Address 0x00 0000 Internal RAM 0x05 0000 FLASH CS0 0x0400 0000 FLASH CS1 0x0800 0000 FLASH CS2 0x0C00 0000 FLASH CS3 0xFF 8000 ROM 0xFF FFFF SDRAM 0x17FF FFFF Reserved 0x2000 0000 Internal SRAM (Frame Buffer) 0x2003 E7FF 0x1000 0000 Byte Address 0x0000 0000
DSP Memory
Shared Memory
Figure 3-3. DSP MMU On
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Functional Overview
3.5
MPU and DSP Private Peripherals
The MPU and DSP each have their own separate private peripheral bus. Peripherals on each of these private buses may only be accessed by their respective processors. For instance, the DSP timers on the DSP private peripheral bus are not accessible by the MPU or the system DMA controller.
3.5.1 Timers
The MPU and DSP each have their own three 32-bit timers available on their respective private TI Peripheral Bus (TIPB). These timers may be configured either in auto-reload or one-shot mode with on-the-fly read capability. The timers generate an interrupt to the respective processor (MPU or DSP) when the timer's down-counter is equal to zero.
3.5.2 Watchdog Timer
The MPU and DSP each have a single watchdog timer. Each watchdog timer can be configured as either a watchdog timer or a general-purpose timer. A watchdog timer requires that the MPU or DSP software or OS periodically write to the appropriate WDT count register before the counter underflows. If the counter underflows, the WDT generates a reset to the appropriate processor (MPU or DSP). The DSP WDT resets only the DSP processor while the MPU WDT resets both processors (MPU and DSP). The watchdog timers are useful for detecting user programs that are stuck in an infinite loop, resulting in loss of program control or in a runaway condition. When used as a general-purpose timer, the WDT is a 16-bit timer configurable either in autoreload or one-shot mode with on-the-fly read capability. The timer generates an interrupt to the respective processor (MPU or DSP) when the timer's down-counter is equal to zero.
PRODUCT PREVIEW
3.5.3 Interrupt Handlers
The MPU and DSP have two levels of interrupt handling each, allowing up to 160 interrupts on the MPU and 98 interrupts on the DSP. This is necessary because of the large number of integrated peripherals on the OMAP5912 device. Some peripherals can generate interrupts to both processors.
3.5.4 CompactFlash Controller (MPU Only)
The CompactFlash controller interfaces a CompactFlash and a classical memory interface. Control signals from the memory interface are processed through the CompactFlash controller to drive a CompactFlash, and control signals from CompactFlash are processed to perform a data transfer to the memory interface. Some pins are shared with common flash memory such as address bus, data bus, and control pins. The CompactFlash controller includes a bypass mode used when common flash memory is connected instead of a CompactFlash card. The CompactFlash module supports the following access modes: * * * Common Memory Attribute Memory I/O
NOTE: True IDE mode is not supported.
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Functional Overview
3.5.5 LCD Controller (MPU Only)
The OMAP5912 device includes an LCD controller that interfaces with most industry-standard LCD displays. The LCD controller is configured by the MPU and utilizes a dedicated channel on the system DMA to transfer data from the frame buffer. The frame buffer can be implemented using external SDRAM via the EMIFF. Using the frame buffer as its data source, the system DMA must provide data to the FIFO at the front end of the LCD controller data path at a rate sufficient to support the chosen display mode and resolution. Optimal performance is achieved when using the internal SRAM as the frame buffer. The panel size is programmable, and can be any width (line length) from 16 to 1024 pixels in 16-pixel increments. The number of lines is set by programming the total number of pixels in the LCD. The total frame size is programmable up to 1024 x 1024; however, clock rate and frame size may be limited by memory bandwidth, which is shared with the MPU and DSP. The screen is intended to be mapped to the frame buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes of words in the frame memory. The principle features of the LCD controller are: * * * * * * * * Dedicated 64-entry x 16-bit FIFO Programmable display including support for 2-, 4-, 8-, 12-, and 16-bit graphics modes Programmable display resolutions up to 1024 pixels by 1024 lines (assuming sufficient system bandwidth) Support for passive monochrome (STN) displays Support for passive color (STN) displays Support for active color (TFT) displays Patented dithering algorithm, providing: - - - - * * * * 15 grayscale levels for monochrome passive displays 3375 colors for color passive displays 65536 colors for active color displays 256-entry x 12-bit palette Dedicated LCD DMA channel for LCD display
Programmable pixel rate Pixel clock plus horizontal and vertical synchronization signals AC-bias drive signal Active display enable signal
3.5.6 LCDCONV (MPU Only)
This module enables to provide a 16-bit to 18-bit LCD data conversion to the LCD interface. It supports two operating modes: * * 16-bit LCD mode 18-bit LCD mode
The mode switching is done by software by setting a dedicated bit in its control register. The software is also able to know which mode is currently in use by looking in a status register. When 16-bit LCD mode is used, the module operates in bypass mode, where all the 16-bit LCD pixel data coming from the frame buffer is directly provided to an external LCD interface. When the 18-bit LCD mode is used, the 16-bit LCD pixel signal is converted to an 18-bit LCD pixel signal through a Red, Green, Blue color (RGB) lookup table. Then the 18-bit LCD pixel format adds a LSB bit to the R (coding Red color) and B (Blue color) signals.
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3.5.7 Random Number Generator (RNG)
The Random Number Generator (RNG) module provides a true, non-deterministic noise source for the purpose of generating keys, Initialization Vectors (IVs), and other random number requirements. It is designed for FIPS 140-1 compliance. It also includes Built-In Self-Test (BIST) logic that allows testing of the randomness of the module output and its compliance with the FIPS 140-1 standard.
Initial Latency After Reset
To make sure that sufficient entropy has been built up in the RNG, it takes 225 (33554432) system clock cycles after RNG reset to produce the first random output. Reading the Random Number Output Register (RNG_OUT) triggers the generation of the next random number, and the busy status bit is set to 1.
Generate Random Number
It takes only 160 system clock cycles to produce each subsequent 32-bit random number once the initial reset latency has been completed. The random numbers are accessible to the application in a 32-bit read-only register (RNG_OUT). Once the register is read, the RNG module immediately generates a new value, which is available after 160 system clock cycles and is then shifted into the output register.
3.5.8 DES/3DES
PRODUCT PREVIEW
The DES3DES security module provides hardware-accelerated data encryption/decryption functions. It can run either the single DES algorithm or the triple DES (TDES or 3DES) algorithm in compliance with the FIPS 46-3 standard. It supports ECB (Electronic Codebook) and CBC (Cipher Block Chaining) modes of operation. It does not support the CFB (Cipher Feedback) and the OFB (Output Feedback) modes of operation in hardware.
3.5.9 SHA1/MD5
The SHA1MD5 security module provides hardware-accelerated hash functions. It can run either the SHA-1 algorithm in compliance with the FIPS 180-1 standard or the MD5 Message-Digest Algorithm developed by R. Rivest in 1991. Up to 227 bytes (128 Mbytes) of data can be hashed in a single operation and will produce a 160-bit signature in the case of SHA-1, and a 128-bit signature in the case of MD5.
3.6
MPU Public Peripherals
Peripherals on the MPU Public Peripheral bus may only be accessed by the MPU and the system DMA controller, which is configured by the MPU. This bus is called a public bus because it is accessible by the system DMA controller. The DSP cannot access peripherals on this bus.
3.6.1 USB Interface
The OMAP5912 processor provides several varieties of USB functionality, including: * * * USB host: OMAP5912 provides a three-port USB Specification Revision 1.1-compliant host controller, which is based on the OHCI Specification for USB Release 1.0a. USB device: OMAP5912 provide a full-speed USB device. USB On-The-Go (OTG): OMAP5912 acts as an OTG dual-role device; the USB device functionality and one port of the USB host controller act in concert to provide an OTG port.
Flexible multiplexing of signals from the OMAP5912 USB host controller, USB function controller, and other peripherals allows for a wide variety of system-level USB capabilities. Many of the OMAP5912 pins can be used for USB-related signals or for signals from other peripherals. The top-level pin multiplexing controls each pin individually and allows for the selection of one of several possible internal pin signal interconnections. When these shared pins are programmed for use as USB signals, the OMAP5912 USB signal multiplexing selects how the signals associated with the three OMAP5912 USB host ports and the OMAP5912 USB function controller can be brought out to OMAP5912 pins.
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The USB host controller (HC) is a three-port controller that communicates with USB devices at low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) data rates. It is compatible with the Universal Serial Bus Specification Revision 2.0 and the OpenHCI - Open Host Controller Interface Specification for USB, Release 1.0a, which is available on the Internet, and is hereafter called the OHCI Specification for USB. It is assumed that users of the OMAP5912 USB host controller are already familiar with the USB Specification and OHCI Specification for USB. The OMAP5912 OTG controller can use one of the USB host controller ports as part of a USB OTG-capable connection. When used for an OTG connection, the host controller port acts as the upstream device when OMAP5912 controls the OTG link, and the USB function controller acts as the downstream device when OMAP5912 acts as an OTG downstream device. The USB host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB. These registers and data structures are the mechanism by which a USB host controller driver software package can control the USB host controller. The OHCI Specification for USB also defines how the USB host controller implementation must interact with those registers and data structures in system memory. The OMAP5912 MPU accesses these registers via the MPU public peripheral bus. NOTE: USB 2.0 hi-speed is not supported.
3.6.2 Display Interface SoSSI
The SoSSI peripheral supports the medium speed screen interface (MeSSI) display interface standard. This peripheral includes a VIA-bus interface converted into TIPB interface connected on the MPU shared peripheral bus, and an interface with the system DMA which enables connection of an extended LCD display to the OMAP5912 device. This peripheral supports multiple frequencies for different displays (maximum output data frequency is 20 MHz). It also provides the capability to program the number of bytes sent to the LCD display. The display interface is a bidirectional parallel interface. It consists of a display data I/O bus (DispDataOut[15:0]), write enable (WRX), read enable (RDX), chip-select (CS), and command/pixel data (A0) signals.
3.6.3 Camera Interface
The camera interface is an 8-bit external port that can be used to accept data from an external camera sensor. This interface can handle multiple image formats synchronized on vertical and horizontal synchronization signals.
The camera interface module converts the 8-bit data transfers into 32-bit words and utilizes a 128-word buffer to facilitate efficient data transfer to memory. Data may be transferred from the camera interface buffer to internal memory by the system DMA controller or directly by the MPU. The interface provides an output reference clock at rates of 6 MHz to 24 MHz from the internal clock (ARM peripheral clock).
3.6.4 Compact Camera Port (CCP)
In addition to the parallel camera interface, OMAP5912 includes a 2-pin differential pair compact camera port interface. This interface is a synchronous serial bus, one data and one clock line. The camera provides one clock, another clock is provided by OMAP5912 to the camera. The CCP interface uses differential signalling, and subLVDS I/Os are needed for that. The CCP is a unidirectional interface. Control information to the camera is transmitted via an I2C Bus.
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3.6.5 MICROWIRE Serial Interface
The MICROWIRE interface is a serial synchronous interface that can drive up to four serial external components. This interface is compatible with the MICROWIRE standard and is seen as the master. MICROWIRE is typically used to transmit control and status information to external peripheral devices or to transmit data to or from small nonvolatile memories such as serial EEPROMs or serial flash devices.
3.6.6 Real-Time Clock (RTC)
The RTC peripheral provides an embedded real-time clock module that can be directly accessible from the MPU. The RTC peripheral is powered independently of the OMAP5912 MPU core power. The RTC module has the following features: * * * Time information (seconds/minutes/hours) directly in BCD code Calendar information (day/month/year/day of the week) directly in BCD code up to year 2099 Interrupts generation, periodically (1s/1m/1h/1d period) or at a precise time of the day (alarm function) 30-s time correction Oscillator frequency calibration
PRODUCT PREVIEW
* *
3.6.7 Pulse-Width Tone (PWT)
The pulse-width tone (PWT) peripheral generates a modulated frequency signal for use with an external buzzer. The frequency is programmable between 349 Hz and 5276 Hz with 12 half-tone frequencies per octave. The volume level of the output is also programmable.
3.6.8 Pulse-Width Light (PWL)
The pulse-width light (PWL) peripheral allows the control of the backlight of the LCD and the keypad by employing a 4096-bit random sequence. This voltage level control technique decreases the spectral power at the modulator harmonic frequencies. The block uses a switchable 32-kHz clock, independent of UPS.
3.6.9 Keyboard Interface
Keyboard is composed of specific MPUIOs dedicated for 8 x 8 keyboard connection: * * Eight inputs (KB.R[7:0]) for row lines Eight outputs (KB.C[7:0]) for column lines
The keyboard feature allows communication with a keyboard. The MPUIO or keyboard interface supports keyboards with up to eight rows and eight columns and has the capability to detect multiple key presses. A keyboard event is signaled to the host by an interrupt.
3.6.10
HDQ/1-Wire Interface
This module allows implementation of both HDQ and 1-Wire protocols. These protocols use a single wire to communicate between a master and a slave. The HDQ/1-Wire pin is open-drain and requires an external pullup resistor. HDQ and 1-Wire interfaces can be found on commercially available battery and power management devices. The interface can be used to send command and monitor its status between OMAP5912 and such devices.
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3.6.11
Multimedia Card/Secure Digital (MMC/SDIO1) Interface
The MMC/SDIO1 host controller provides an interface between the MPU and MMC/SD/SDIO memory cards plus up to four serial flash cards, and it also handles MMC/SDIO or SPI transactions with minimum local host intervention. The following combinations of external devices are supported: * * One or more MMC memory cards sharing the same bus and up to four devices with 8-bit SPI protocol interface (serial flash memories, etc.) One single SD memory card or SDIO card and up to four devices with 8-bit SPI protocol interface
The application interface is responsible for managing transaction semantics; the MMC/SDIO1 host controller deals with MMC/SDIO protocol at transmission level, packing data, adding CRC, start/end bit and checking for syntactical correctness. SD mode wide bus width is also supported (1- or 4-bit data lines). The application interface can send every MMC/SDIO command and either poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to notify for end of operations. The application interface can read card responses or flag register. It can also mask individually interrupt sources. All these operations can be performed reading and writing control registers. The MMC/SDIO1 peripheral also supports two DMA channels.The main features of the MMC/SDIO1 module are: * * * * * * * * * * Full compliance with MMC command/response sets as defined in the MMC standard specifications v.3.1 Full compliance with SDIO command/response sets as defined in the SDIO card specification v1.0 Flexible architecture, allowing support for new command structure Built-in 64-byte FIFO for buffered read or write 16-bit-wide access bus to maximize bus throughput Designed for low power Wide interrupt capability Programmable clock generation Two DMA channels NOTE: The MMC/SDIO1 interface includes all the MMC/SDIO pins except the direction controls (data and control).
3.6.12
MPUIO Interface
The MPUIO feature allows communication with an external device through as many as 16 MPUIOs. These MPUIOs can be configured on a pin-by-pin basis as inputs or outputs. When configured as input, each MPUIO can be individually selected to generate interrupts on a level change (rising or falling edge). In normal operation, the MPUIO inputs are latched at the falling edge of 32 kHz. In event capture mode, one of the MPUIO inputs can be assigned a clock source, and all the other inputs are latched on its falling edge. The MPUIO module functional clock domain is clocked by the OMAP5912 32-kHz clock. This clock is always fed into the block, regardless of the state of the chip (awake, asleep, or idle). This allows external event latching and interrupt generation even when the system is in idle mode, to wake up the system via interrupt. The MPUIO module interfaces with the host through a TIPB bus. The MPU peripheral clock resynchronizes register access to the module and avoids time-out on the TIPB bus caused by the functional clock being too slow.
3.6.13
LED Pulse Generators (LPG)
There are two separate LED pulse generator (LPG) modules. Each LPG module provides an output for an indication LED. The blinking period is programmable between 152 ms and 4 s or the LED can be switched on or off permanently.
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Full compliance with SD command/response sets as defined in the SD physical layer specifications v.1.0
Functional Overview
3.6.14
Frame Adjustment Counter (FAC)
The frame adjustment counter (FAC) is a simple peripheral that counts the number of rising edges of one signal (start of frame interrupt of the USB function) during a programmable number of rising edges of a second signal (transmit frame synchronization of McBSP2). The FAC may only be used with these specific USB Function and McBSP2 signals. The count value can be used by system-level software to adjust the duration of the two time domains with respect to each other to reduce overflow and underflow. If the data being transferred is audio data, this module can be part of a solution that reduces pops and clicks. The FAC module generates one second-level interrupt to the MPU.
3.6.15
Operating System (OS) Timer
A programmable interval timer is required to generate a periodic interrupt, also called system clock tick, to the OS. This is used to keep track of the current time and to control the operation of device drivers. Key functions are: * * * * * Read current value of the timer Generate interrupt as the timer down-counts to zero Reset the interrupt by writing an 1 to the interrupt bit in the control register Timer interrupt period: Irq_rate = (Tick_value_reg + 1) / 32768 Maximum tick value register is 0xFFFF, so maximum timer interrupt period is 2 sec.
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3.7
DSP Public Peripherals
Peripherals on the DSP Public Peripheral bus are directly accessible by the DSP and DSP DMA. These peripherals may also be accessed by the MPU and System DMA Controller via the MPUI interface. The MPUI interface must be properly configured to allow this access.
3.7.1 Multichannel Buffered Serial Ports (McBSP1 and 3)
The multichannel buffered serial port (McBSP) provides a high-speed, full-duplex synchronous serial port that allows direct interface to audio codecs and various other system devices. The DSP public peripheral bus has access to two McBSPs: McBSP1 and McBSP3. NOTE: All of the standard McBSP pins are not necessarily available on every McBSP on the OMAP5912 devices. In the case of the two DSP McBSPs, the following pins are available: McBSP1 pins: * * * * CLKX (data bit clock) FSX (data bit frame sync)
CLKS (external reference to sample rate generator)
McBSP3 pins: * * * CLKX (transmit clock) FSX (transmit frame sync) DX and DR (transmit and receive data)
CLKX and FSX of McBSP1 and McBSP3 are used for both transmitting and receiving. The functional clock to the McBSP1 and McBSP3 is fixed at the OMAP5912 base operating frequency (12, 13, or 19.2 MHz). The bit-clock rate for these McBSPs is therefore limited to 6, 6.5, or 9.6 MHz (one half the base frequency). Only McBSP1 has the CLKS pin available. If the sample rate generator (SRG) is used on McBSP1, the reference clock to the SRG can be configured to be either an external reference provided on the CLKS pin, or the internal base (12, 13, or 19.2-MHz) device clock. However, if the SRG is used on McBSP3, the only reference clock available to this SRG is the base device clock as clock reference.
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DX and DR (transmit and receive data)
Functional Overview
3.7.2 Multichannel Serial Interfaces (MCSI1 and 2)
The MCSI provides a flexible serial interface with multichannel transmission capability. The MCSI allows the DSP to access a variety of external devices, such as audio codecs and other types of analog converters. The DSP public peripheral bus has access to two MCSIs: MCSI1 and MCSI2. These MCSIs provide full-duplex transmission and master or slave clock control. All transmission parameters are configurable to cover the maximum number of operating conditions. The MCSIs have the following features: * Master or slave clock control (transmitter clock and frame synchronization pulse) - - * * * * Programmable transmitter clock frequency in master mode of up to one half the OMAP5912 base frequency (12,13, or 19.2 MHz) Receiver clock frequency in slave mode of up to the base frequency (12,13, or 19.2 MHz)
Single-channel or multichannel (x16) frame structure Programmable word length: 3 to 16 bits Full-duplex transmission Programmable frame configuration - - - - - - Continuous or burst transmission Normal or alternate framing Normal or inverted frame and clock polarities Short or long frame pulse Programmable oversize frame length Programmable frame length
PRODUCT PREVIEW
*
Programmable interrupt occurrence time (TX and RX) - - Error detection with interrupt generation on wrong frame length System DMA support for both TX and RX data transfers
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3.8
Shared Peripherals
The shared peripherals are connected to both the MPU Public Peripheral bus and the DSP Public Peripheral bus. Connections are achieved via a TI Peripheral Bus Switch, which must be configured to allow MPU or DSP access. The other shared peripherals have permanent connections to both public peripheral buses, although read and write accesses to each peripheral register may differ.
3.8.1 Mailboxes
Four sets of shared mailbox registers are available for communication between the DSP and MPU: * * Two read/write accessible by MPU, read-only by the DSP Two read/write accessible by the DSP, read-only by the MPU
3.8.2 General-Purpose Timers
OMAP5912 consists of eight 32-bit timers with the following features: * * * * * * * * * * * Counter timer with compare and capture modes Autoreload mode Start-stop mode Programmable divider clock source 16-/32-bit addressing On-the-fly read/write registers Interrupts generated on overflow, compare, and capture Interrupt enable Wake-up enable Write posted mode Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
Each timer module contains a free-running upward counter with autoreload capability on overflow. The timer counter can be read and written on-the-fly (while counting). The timer module includes compare logic to allow interrupt event on programmable counter matching value. A dedicated output signal can be pulsed or toggled on overflow and match event. This offers timing stamp trigger signal or PWM (pulse width modulation) signal sources. A dedicated input signal can be used to trigger automatic timer counter capture and interrupt event, on programmable input signal transition type. A programmable clock divider (prescaler) allows reduction of the timer input clock frequency. All internal timer interrupt sources are merged into one module interrupt line and one wake-up line. Each internal interrupt sources can be independently enabled/disabled with a dedicated bit of the TIER register for the interrupt features and a dedicated bit of TWER for the wake-up.
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Functional Overview
Each timer has three possible clock sources: * * * * the 32-kHz clock the system clock an external clock source NOTE: Three of the eight dual-mode timer PWM outputs are connected at OMAP5912 I/Os. Two of the eight dual-mode timer input capture are connected at OMAP5912 I/Os. The system clock can come either from OMAP or directly from the input clock. Can wake up the system when the clock is configured as 32-kHz through its own interrupt through a general-purpose timer
*
3.8.3 Serial Port Interface (SPI)
The serial port interface is a bidirectional, four-line interface dedicated to the transfer of data to and from external devices offering a four-line serial interface. The four-line interfaces are: * the clock used to shift-in and shift-out data the device enable the data input the data output
PRODUCT PREVIEW
* * *
This serial port interface is based on a looped shift-register, thus allowing both transmit and receive modes. It can operate either in master or slave mode, using MPU or DMA control. In master mode, the SPI provides up to five chip-selects; four of them are for external devices. In slave mode, the SPI has its own chip-select. In master mode, the maximum SPI data rate is the same as the system clock frequency; in slave mode, the clock of the serial data out is provided by an external device at lower data rate.
3.8.4 Universal Asynchronous Receiver/Transmitter (UART)
The OMAP5912 includes three universal asynchronous receiver/transmitter (UART) peripherals which are accessible on the DSP public and MPU public peripheral buses. The MPU configures the UART's owner processor (MPU or DSP). All three UARTs are standard 16C750-compatible UARTs implementing an asynchronous transfer protocol with various flow control options. UART1 and UART3 can function as general UART or can optionally function as IrDA interface. The clock source for the UART1 and UART3 is: * APLL output
The clock source for the UART2 can be: * * system clock or the sleep clock APLL output
The main features of the UART peripherals include: * * * Selectable UART/autobaud modes Dual 64-entry FIFOs for received and transmitted data payload Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation
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* * * * * * *
Programmable sleep mode Complete status-reporting capabilities in both normal and sleep mode Frequency prescaler values from 0 to 65535 to generate the appropriate baud rates Interrupt request generated if multiple system DMA requests Baud rate from 300 bits/s up to 1.5M bits/s Autobauding between 1200 bits/s and 115.2K bits/s Software/hardware flow control - - Programmable XON/XOFF characters Programmable auto-RTS and auto-CTS
*
Programmable serial interface characteristics - - - - - 5-, 6-, 7-, or 8-bit characters Even-, odd-, or no-parity bit generation and detection 1, 1.5, or 2 stop-bit generation False start bit detection Line break generation and detection
* *
Internal test and loopback capabilities Modem control functions (CTS, RTS, DSR, DTR) NOTE: DSR and DTR are not available on UART2.
The key features of the IrDA mode (UART1 and 3) are: * * * * * * * Support of slow infrared (SIR) configuration (baud rate up to 115.2Kbauds) Support of medium infrared (MIR) configuration (baud rate 0.576Mbits/s, and 1.152Mbits/s in the following range [1.1508Mbits/s to 1.1532Mbits/s]) Support of fast infrared (FIR) configuration (baud rate at 4Mbauds, the effective frequency baud rate is 8Mbits/s in the following range [7.9992Mbits/s to 8.0008Mbits/s]) Frame formatting: addition of variable xBOF characters and EOF characters Uplink/downlink CRC generation/detection Asynchronous transparency (automatic insertion of break character) 8-entry status FIFO available to monitor frame length and frame errors
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3.8.5 I 2C Master/Slave Interface
The multimaster I2C peripheral provides an interface between a local host (LH), such as an MPU or DSP processor, and any I2C bus compatible device that connects via the I2C serial bus. External components attached to the I2C bus can serially transmit/receive up to 8 bits of data to/from the LH device or a DMA through the I2C interface. This I2C peripheral supports any slave or master I2C-compatible device. The I2C bus is a multimaster bus. The I2C controller supports the multimaster mode, which allows more than one device capable of controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can operate as either transmitter or receiver, depending on the function of the device. In addition to being a transmitter or receiver, the device connected to the I2C bus can also be considered a master or a slave when performing data transfers. Note that a master device is the device which initiates a data transfer on the bus and generates the clock signals to enable that transfer. During the latter, any device addressed by this master is considered a slave. The I2C interface with the local host is compliant with 8-/16-bit OCP protocol. The interface clock and the functional clock are independent. The I2C master/slave interface supports the following features: * Compliant to Philips I2C-bus specification version 2.1 Support standard mode (up to 100K bits/s) and fast mode (up to 400K bits/s) In the master only I2C operating mode of OMAP5912, standard mode is supported up to 83K bits/s. 7-bit and 10-bit device addressing modes General call Start/restart/stop Multimaster transmitter/slave receiver mode Multimaster receiver/slave transmitter mode Combined master transmit/receive and receive/transmit mode Built-in FIFO for buffered read or write Module enable/disable capability Programmable clock generation Supports use of two DMA channels
PRODUCT PREVIEW
* * * * * * * * * * * *
The I2C master/slave interface does not support the following features: * * High-speed (HS) mode for transfer rates up to 3.4M bits C-bus compatibility mode
3.8.6 Multichannel Buffered Serial Port (McBSP2)
The multichannel buffered serial port (McBSP) provides a high-speed, full-duplex serial port that allows direct interface to audio codecs, and various other system devices. The McBSP provides: * * * Full-duplex communication Double-buffer data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit
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In addition, the McBSP has the following capabilities: * Direct interface to: - - - - - - * * * * * T1/E1 framers MVIP switching-compatible and ST-BUS compliant devices IOM-2 compliant device AC97-compliant device I2S-compliant device Serial peripheral interface (SPI)
Multichannel transmit and receive of up to 128 channels per frame A variety of data sizes, including: 8, 12, 16, 20, 24, or 32 bits -law and A-law companding Programmable polarity for both frame synchronization and data clocks
NOTE: All of the standard McBSP signals are not necessarily available on every McBSP on the OMAP5912 device. In the case of the MPU McBSP2, the following pins are available: * * * CLKX and CLKR (transmit and receive clocks) FSX and FSR (transmit and receive frame syncs) DX and DR (transmit and receive data)
The functional clock to the McBSP2 peripheral is configurable to the DPLL clock rate with a divider of 1, 2, 4, or 8. McBSP2 does not have a CLKS external clock reference pin. Therefore, if the McBSP2 sample rate generator (SRG) is used, the only reference clock available to the SRG is a programmable clock from the MPU domain.
3.8.7 Multimedia Card/Secure Digital (MMC/SDIO2) Interface
The MMC/SDIO2 host controller provides an interface between a local host (such as the MPU/DSP and MMC/SD/SDIO memory cards) plus up to four serial flash cards, and handles MMC/SDIO or SPI transactions with minimum local host intervention. The following combinations of external devices are supported: * * One or more MMC memory cards sharing the same bus and up to four devices with 8-bit SPI protocol interface (serial flash memories, etc.) One single SD memory card or SDIO card and up to four devices with 8-bit SPI protocol interface
The application interface is responsible for managing transaction semantics; the MMC/SDIO2 host controller deals with MMC/SDIO protocol at transmission level, packing data, adding CRC, start/end bit and checking for syntactical correctness. SD mode wide bus width is also supported (1- or 4-bit data lines). The application interface can send every MMC/SDIO command and either poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn for end of operations. The application interface can read card responses or flag register. It can also mask individually interrupt sources. All these operations can be performed reading and writing control registers. The MMC/SDIO2 peripheral also supports two DMA channels.
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Programmable internal clock and frame generation
Functional Overview
The main features of the MMC/SDIO2 module are: * * * * * * * * * * * Full compliance with MMC command/response sets as defined in the MMC standard specifications v.3.1 Full compliance with SD command/response sets as defined in the SD physical layer specifications v.1.0 Full compliance with SDIO command/response sets as defined in the SDIO card specification v1.0 Flexible architecture, allowing support for new command structure Built-in 64-byte FIFO for buffered read or write 16-bit-wide access bus between MMC/SDIO2 interface and the local hosts to maximize bus throughput Designed for low power Wide interrupt capability Programmable clock generation Two DMA channels OMAP5912 also support control signals to external level shifters. These signals are derived from the direction control of the MMC_DAT0 and MMC_CMD I/O pads (one direction control per data bit line and one direction control for the command line). NOTE: * * * The MMC/SDIO2 clock is multiplexed between the 48-MHz clock (APLL output) and the system clock (19.2 MHz or 12 MHz). At reset, the MMC/SDIO2 clock selection is the system clock. The MMC/SDIO2 module is routed at the OMAP5912 level. The OMAP5912 configuration selects only the part of the interface which is required.
PRODUCT PREVIEW
3.8.8 General-Purpose I/O (GPIO)
OMAP5912 includes 4 GPIO peripherals of 16 GPIO pins each. There are up to 64 shared GPIO pins. Each GPIO pin is independently configurable as either input or output. If configured as input, each pin can be configurable to generate an interrupt upon detection of its signal level change. As both the MPU and the DSP can access the GPIO, consideration must be taken for its arbitration. The general-purpose input/output (GPIO) peripheral can be used for the following types of applications: * * * Input/output data Generation of an interrupt in active mode upon the detection of external events Generation of a wake-up request in idle mode upon the detection of external events
3.8.9 32-kHz Synchro Counter
This is a 32-bit ordinary counter, clocked by the falling edge of the 32-kHz clock. It is reset while the Power Up Reset (PWRON_RESET) primary I/O is active (main OMAP5912 reset), then on the rising edge of PWRON_RESET (PWRON_RESET release), it starts to count indefinitely. When the highest value is reached, it wraps back to zero and starts running again. MPU and DSP have the capability to read the count value at higher frequency from the peripheral interface. The MPU can read it from a 32-bit peripheral access, whereas the DSP can only access it through two consecutive 16-bit accesses.
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3.8.10
VLYNQ Interface
VLYNQ is a serial (that is, low pin count) communications interface that enables the extension of an internal bus segment to one or more external physical devices. The external devices are mapped into local, physical address space and appear as if they are on the internal bus of the OMAP5912. The external devices must also have a VLYNQ interface. The VLYNQ module serializes bus transactions in one device, transfers the serialized data between devices via a VLYNQ port, and de-serializes the transaction in the external device. OMAP5912 includes one VLYNQ module connected on OCPT2 target port and OCPI initiator port. These connections are configured via a static switch, which selects either SSI or VLYNQ module. This switch forbids the simultaneous use of GDD/SSI and VLYNQ. One typical VLYNQ application of OMAP processors is to open a communication channel with TI wireless LAN 802.11.x base band processors like TNET1130 and TNET1230. NOTE: The OMAP5912 VLYNQ channel with TNET1130 or TNET1230 is optimized if OMAP5912 generates the serial clock : - - Maximum serial clock frequency if received as external signal is 80 MHz.
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Maximum serial clock frequency if transmitted and internally generated is 100 MHz.
Functional Overview
3.9
System DMA Controller
The system direct memory access (DMA) controller transfers data between points in the memory space without intervention by the MPU. The system DMA allows movements of data to and from internal memory, external memory, and peripherals to occur in the background of MPU operation. It is designed to off-load the block data transfer function from the MPU processor. The system DMA is configured by the MPU via the MPU private peripheral bus. System DMA consists of: * * * Seventeen logical channels Seven physical ports + one for configuration Four physical channels
PRODUCT PREVIEW
The ports are connected to the L3 OCP targets, the external memory, the TIPB bridge, the MPUI, and one dedicated port connected to an LCD controller. The system DMA controller can be controlled via the MPU private TIPB or by an external host via the OCP-I port. The system DMA controller is designed for low-power operation. It is partitioned into several clock domains where each clock domain is enabled only when it is used. All clocks are disabled when no DMA transfers are active (synchronous to the MPU TIPB, this feature is totally under hardware control; no specific programming is needed). Five different logical channels types are supported; each one represents a specific feature set: * * * * * * LCh-2D for memory-to-memory transfers, 1D and 2D LCh-P for peripheral transfers LCh-PD for peripheral transfers on a dedicated channel LCh-G for graphical transfers/operations LCh-D for display transfers
The available features are: Support for up to four address modes: - - - - * * * * * * * * * * * Constant Post-increment Single indexing Double indexing
Different indexing for source-respective destination Logical channel chaining Software enabling Hardware enabling Logical channel interleaving Logical channel preemption Two choices of logical channel arbitration of physical resources: round robin or fixed Two levels of logical channel priority Constant fill Transparent copy Rotation 0, 90, 180, and 270
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Functional Overview
There are seven ports enabling: * * * * * * Memory-to-memory transfers Peripheral-to-memory transfers Memory-to-peripheral transfers Peripheral-to-peripheral transfers Binary backward-compatible by default configuration Up to four logical channels active in parallel
The logical channel dedicated to the display, LCh-D, has several additional features: * * * Channel can be shared by two LCD controllers Supports both single- and dual-block modes Supports separate indexing and numbering for dual-block mode for both elements and frames
3.10 DSP DMA Controller
The DSP subsystem has its own dedicated DMA controller, which is entirely independent of the MPU or the system DMA controller. The DSP DMA controller has many of the same major features as the system DMA controller. The DSP DMA Controller has six generic channels and five physical ports available for source or destination data. These five ports are the SARAM port, DARAM port, EMIF (external memory port), DSP TIPB port, and MPUI port. The DSP may configure the DSP DMA controller to transfer data between the SARAM, DARAM, EMIF, and TIPB ports; but the MPUI port is a dedicated port used for MPU or system DMA initiated transfers to DSP subsystem resources. The SARAM and DARAM ports are used to access local DSP memories and the TIPB port is used to access the registers of the DSP peripherals. The EMIF port of the DSP DMA controller is used to access the Traffic Controller via the DSP MMU (Memory Management Unit).
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Functional Overview
3.11 Traffic Controller (Memory Interfaces)
The traffic controller (TC) manages all accesses by the MPU, DSP, system DMA, and local bus to the OMAP5912 system memory resources. The TC provides access to three different memory interfaces: external memory interface slow (EMIFS), external memory interface fast (EMIFF), and internal memory interface (OCP T1). The OCP T1 allows access to the 250K bytes of on-chip frame buffer. The EMIFS provides 16-bit-wide access to asynchronous or synchronous memories or devices, including the following: * * * * * * * * Intel fast boot block flash (23FxxxF3) AMD simultaneous read/write boot sector flash (AM29DLxxxG) AMD burst-mode flash (AM29BLxxxC) Intel StrataFlash memory (28FxxxJ3A) Intel synchronous StrataFlash memory (28FxxxK3/K18) Intel wireless flash memory (28FxxxW18) Samsung NAND Flash (K9F56xxQ0M) Asynchronous SRAM
PRODUCT PREVIEW
The EMIFF provides access to 16-bit-wide access to mobile SDRAM and DDR memories, including the following: * * Mobile SDRAM (Elpida EDLxxxCBB, Infineon HYExxLxxx, Samsung K4Mxxxxx) Mobile DDR (Elpida EDKxxxCBB, Samsung K4Xxxxxx)
The TC provides the functions of arbitrating contending accesses to the same memory interface from different initiators (MPU, DSP, system DMA, local bus), synchronization of accesses due to the initiators and the memory interfaces running at different clock rates, and the buffering of data allowing burst access for more efficient multiplexing of transfers from multiple initiators to the memory interfaces. The TC architecture allows simultaneous transfers between initiators and different memory interfaces without penalty. For instance, if the MPU is accessing the EMIFF at the same time the DSP is accessing the IMIF, transfers may occur simultaneously since there is no contention for resources. There are three separate ports to the TC from the system DMA (one for each of the memory interfaces), allowing for greater bandwidth capability between the system DMA and the TC.
AMD is a trademark of Advanced Micro Devices, Inc. Intel StrataFlash is a registered trademark of Intel Corporation. Samsung is a trademark of Samsung Corporation. Elpida is a trademark of Elpida Memory, Inc. Infineon is a trademark of Infineon Technologies AG Corporation.
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Functional Overview
3.12 Interprocessor Communication
Several mechanisms allow for communication between the MPU and the DSP on the OMAP5912 device. These include mailbox registers, MPU Interface, and shared memory space.
3.12.1
MPU/DSP Mailbox Registers
The MPU and DSP processors can communicate with each other via a mailbox-interrupt mechanism. This mechanism provides a very flexible software protocol between the processors. There are four sets of mailbox registers located in public TIPB space. The registers are shared between the two processors, so the MPU and DSP may both access these registers within their own public TIPB space, but read/write accessibility of each register is different for each processor. There are four sets of mailbox registers: two for the MPU to send messages and issue an interrupt to the DSP, the other two for the DSP to send messages and issue an interrupt to the MPU. Each set of mailbox registers consists of two 16-bit registers and a 1-bit flag register. The interrupting processor can use one 16-bit register to pass a data word to the interrupted processor and the other 16-bit register to pass a command word. Communication is achieved when one processor writes to the appropriate command word register, which causes an interrupt to the other processor and sets the appropriate flag register. The interrupted processor acknowledges by reading the command word, which causes the flag register to be cleared. An additional data-word register is also available in each mailbox register set to optionally communicate two words of data between the processors for each interrupt instead of just communicating the command word. The information communicated by the command and data words are entirely user-defined. The data word can be optionally used to indicate an address pointer or status word.
3.12.2
MPU Interface (MPUI)
The MPU interface (MPUI) allows the MPU and the system DMA controller to communicate with the DSP and its peripherals. The MPUI allows access to the full memory space (16M bytes) of the DSP and the DSP public peripheral bus. Thus, the MPU and system DMA controller both have read and write access to the complete DSP I/O space (128K bytes), including the control registers of the DSP public peripherals. The MPUI port supports the following features: * Four access modes: - - - - * * * * * * * Single-access mode (SAM) for MPU access of DSP SARAM, DARAM, and external memory interface Single-access mode (SAM) for peripheral bus access Host-only mode (HOM) for SARAM access Host-only mode (HOM) for peripheral bus access
Interrupt to MPU if access time-out occurs Programmable priority scheme (MPU versus DMA) Packing and unpacking of data (16 bits to 32 bits, and vice versa) 32-bit single-access support Software control endianism conversion System DMA capability to full memory space (16M bytes) System DMA capability to the DSP public TIPB peripherals (up to 128K bytes space)
This port can be used for many functions, such as: MPU loading of program code into DSP program memory space, sharing of data between MPU and DSP, implementing interprocessing communication protocols via shared memory, or allowing MPU to use and control DSP public TIPB peripherals.
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Functional Overview
3.12.3
MPU/DSP Shared Memory
The OMAP5912 implements a shared memory architecture via the traffic controller. Therefore, the MPU and DSP both have access to the same shared SRAM memory (frame buffer of 250K bytes) as well as to the EMIFF and EMIFS memory space. Through the DSP memory management unit (MMU), the MPU controls which regions of shared memory space the DSP is allowed to access. By setting up regions of shared memory, and defining a protocol for the MPU and DSP to access this shared memory, an interprocessor communication mechanism may be implemented. This method can be used in conjunction with the mailbox registers to create handshaking interrupts that properly synchronize the MPU and DSP accesses to shared memory. Utilizing the shared memory in this fashion may be useful when the desired data to be passed between the MPU and DSP is larger than the two 16-bit words provided by each set of mailbox command and data registers. For example, the MPU may need to provide the DSP with a list of pointers to perform a specific task as opposed to a single command and single pointer. Using shared memory and the mailboxes, the DSP can read the list of pointers from shared memory after receiving the interrupt caused by an MPU write to the mailbox command register.
3.13 DSP Hardware Accelerators
PRODUCT PREVIEW
The TMS320C55x DSP core within the OMAP5912 device utilizes three powerful hardware accelerator modules which assist the DSP core in implementing specific algorithms that are commonly used in video compression applications such as MPEG4 encoders/decoders. These accelerators allow implementation of such algorithms using fewer DSP instruction cycles and dissipating less power than implementations using only the DSP core. The hardware accelerators are utilized via functions from the TMS320C55x Image/Video Processing Library available from Texas Instruments. Utilizing the hardware accelerators, the Texas Instruments Image/Video Processing Library implements many useful functions, which include the following: * * * * * * * Forward and Inverse Discrete Cosine Transform (DCT) (used for video compression/decompression) Motion Estimation (used for compression standards such as MPEG video encoding and H.26x encoding) Pixel Interpolation (enabling high-performance fractal-pixel motion estimation) Quantization/Dequantization (useful for JPEG, MPEG, H.26x Encoding/Decoding) Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards) Boundary and Perimeter Computation (useful for Machine Vision applications) Image Threshold and Histogram Computations (useful for various Image Analysis applications)
3.13.1
DCT/iDCT Accelerator
The DCT/iDCT hardware accelerator is used to implement Forward and Inverse DCT (Discrete Cosine Transform) algorithms. These DCT/iDCT algorithms can be used to implement a wide range of video compression standards including JPEG Encode/Decode, MPEG Video Encode/Decode, and H.26x Encode/Decode.
3.13.2
Motion Estimation Accelerator
The Motion Estimation hardware accelerator implements a high-performance motion estimation algorithm, enabling MPEG Video encoder or H.26x encoder applications. Motion estimation is typically one of the most computation-intensive operations in video-encoding systems.
3.13.3
Pixel Interpolation Accelerator
The Pixel Interpolation Accelerator enables high-performance pixel-interpolation algorithms, which allows for powerful fractal pixel motion estimation when used in conjunction with the Motion Estimation Accelerator. Such algorithms provide significant improvement to video-encoding applications.
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Functional Overview
3.14 Power Supply Connection Examples 3.14.1 Core and I/O Voltage Supply Connections
The OMAP5912 device is extremely flexible regarding the implementation of the core and I/O voltage supplies of the device. In a typical system, all of the core voltage supplies (CVDDx) may be connected together and powered from one common supply. Likewise, all of the I/O voltage supplies (DVDDx) may be connected together and powered from a common supply. Figure 3-4 illustrates this common system configuration.
OMAP5912 1.5-V Voltage Supply CVDD CVDD1 CVDD2 CVDD3 CVDDA CVDDRTC CVDDDLL 2.75-V Voltage Supply DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 1.8-V Voltage Supply DVDD8 DVDD9 DVDDRTC VSS
NOTE: In this example, SDRAM (DVDD4) and FLASH (DVDD5) I/O voltage supplies are connected to 1.8 V and the other I/O voltage supplies are connected to 2.75 V. But all the I/O voltage supplies (DVDDx) are dual-voltage capable and all power combinations are possible.
Figure 3-4. Supply Connections for a Typical System In the previous example, all CVDDx pins are connected in common. However, the OMAP5912 has dedicated CVDD pins that supply power to different sections of the chip. This feature can be useful in prototyping phases to troubleshoot power management features and perform advanced power analysis. By isolating each CVDDx bus from the power source through isolation jumpers or current sense resistors, the current draw into different domains may be measured separately. This type of supply isolation must only be done during prototyping as production system designs should connect all the CVDDx pins together, preferably to a common board plane. NOTE: There is no specific power sequencing for the different voltage supplies as long as all CVDDx and DVDDx voltages are ramped to valid operating levels within 500 ms of one another. Additionally, if certain I/O pins are unused in a specific system application, the DVDDx supply pins that power these I/O must still be connected to valid operating voltage levels.
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Functional Overview
3.14.2
Core Voltage Noise Isolation
Two CVDD pins on OMAP5912, CVDDA and CVDDDLL, are dedicated to supply power for the ULPD APLL and for the DDL elements of the DDR interface, respectively. In addition to using sound board design principles, these dedicated pins allow for added supply noise isolation circuitry to enable maximum performance. An example circuit is shown in Figure 3-5.
OMAP5912 System Clock Oscillator#
ULPD APLL
DLLs (DDR)
OMAP DPLL
LDO
VSS
CVDDA
CVDDDLL R1 10 W
CVDDX
LDO.FILTER C3 1 mF
PRODUCT PREVIEW
C1 100 nF
Voltage Regulator C2 100 nF R2 10 W
NOTES: A. This circuit is provided only as an example. Specific board layout implementation must minimize noise on the OMAP5912 voltage supply pins. B. Unless otherwise noted in this document, all VSS pins on the OMAP5912 are common and must be connected directly to a common ground; however, the discrete capacitor in the RC filter circuit should be placed as close as possible to the VSS pins [ZZG balls AA21 (or W20) and A13; ZDY balls L7 (or L11) and F6]. C. For special consideration with respect to the connection of VSS pin (ZZG ball Y13; ZDY ball H8), refer to Section 5.6.1, 32-kHz Oscillator and Input Clock. The voltage regulator must be selected to provide a voltage source with minimal low frequency noise. If a dedicated voltage regulator is not available for CV DDDLL in the system, a simple low-pass RC filter can be used to isolate the cells from the switching noise of other digital circuits. Common CV DD for rest of chip. A regulated supply is delivered to DPLL macro(s) and available on unique bond pad. A decoupling capacitor of 1 F must be connected externally between the pin called LDO. FILTER (ZZG ball J1; ZDY ball H1) and the ground. # System clock oscillator frequency = 12, 13, or 19.2 MHz.
Figure 3-5. External RC Circuits for Noise Isolation
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Documentation Support
4
Documentation Support
Extensive documentation supports all OMAP platform of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the OMAP platform of applications processor devices: * * * Device-specific data sheets Development-support tools Hardware and software application reports
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Information regarding Texas Instruments (TI) OMAP and DSP products is also available on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
4.1
Device and Development-Support Tool Nomenclature
Device development evolutionary flow: TMX TMP TMS Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320 is a trademark of Texas Instruments. 171
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To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the OMAP5912 device. All electrical and switching characteristics in this data manual are valid over the recommended operating conditions unless otherwise specified.
5.1
Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating ambient temperature. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.2, Recommended Operating Conditions, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage values (core and I/O) are with respect VSS. This section provides the absolute maximum ratings for the OMAP5912 device.
PRODUCT PREVIEW
Supply voltage range (core), CVDD, CVDD1/2/3/A, CVDDRTC, CVDDDLL . . . . . . . . . . . . . . . . . . . -0.5 V to 1.8 V Supply voltage range (I/O), DVDD1/2/3/4/5/6/7/8/9/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Input voltage range, VI (12,13, or 19.2-MHz and 32-kHz oscillator) . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Input voltage range, VI (Standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Input voltage range, VI (USB Transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Input voltage range, VI (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.5 V Output voltage range, VO (Standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Output voltage range, VO (USB Transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Output voltage range, VO (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.5 V Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
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5.2
Recommended Operating Conditions
MIN NOM 1.1 1.6 1.6 1.6 1.8 2.75 or 3.3 1.8 3.3 MAX 1.21 1.65 1.65 1.65 1.95 3.6 1.95 V 3 3.6 TBD TBD Low-power standby mode Active mode 1.05 1.43 1.1 1.5 0 Standard LVCMOS ZZG balls P9 and R8 (ZDY balls T2 and U1) are not used for USB differential voltage 0.7 DVDD 2 V 1.21 1.65 V V V V V V V UNIT V Low-power standby mode Active mode 1.05 1.52 1.35 1.43 1.65 2.5 1.65
CVDD1/2/3/RTC CVDDA CVDDDLL DVDD1/2/3/4/5/6/7/8/9/RTC
OMAP5912 supply voltage, core Supply voltage for analog PLL
Core supply voltage for the DDR interface digitally controlled delay element (DCDL) Device supply voltage, I/O Low-voltage range# High-voltage range# Internal USB transceiver not used
DVDD2
Device supply voltage, I/O
Internal USB transceiver used
CVDD - DVDD DVDD - CVDD LDO.FILTERk Vss
Device supply voltage difference|| Device supply voltage difference||
Device supply voltage, GND
VIH
High-level input voltage, I/O
ZZG balls W13, W14, Y12, and Y14 (ZDY balls N9, P11, P10, and T12) are not used for CCP differential voltage Standard LVCMOS ZZG balls P9 and R8 (ZDY balls T2 and U1) are not used for USB differential voltage
0.7 DVDD
0.3 DVDD 0.8 V
VIL
Low-level input voltage, I/O
ZZG balls W13, W14, Y12, and Y14 (ZDY balls N9, P11, P10, and T12) are not used for CCP differential voltage
0.3 DVDD

All core voltage supplies must be tied to the same voltage level (within 50 mV). In Split-power mode (CVDDx and DVDDx = 0), RTC has to be supplied with CVDDRTC = 1.05 V min and DVDDRTC = 1.65 V min. Low-power standby is defined as follows: the device is in deep-sleep mode and LOW_PWR = 1. The device runs from 32-kHz clock in this mode. To filter switching noises, it is recommended that an RC (R = 10 , C = 100 nF) low-pass filter be implemented externally. # Corresponding DV DD mode bit must be configured in the Voltage_control_0 register. || In systems where the CV DDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between CVDD and DVDD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DVDDx supplies, all DVDDx supplies should be ramped up to valid voltage levels within 500 ms of one another. kAn external capacitor (C = 1 F 10%) must be connected between LDO.FILTER and VSS to provide decoupling capacitance for the regulator. hLDO has to be powered down by setting LDO_PWRDN_CNTL[0] in OMAP5912 configuration.
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PRODUCT PREVIEW
Internal DPLL and 12, 13, or 19.2-MHz oscillator supply voltageh
Electrical Specifications
5.2
Recommended Operating Conditions (Continued)
MIN ZZG balls P9 and R8 (ZDY balls T2 and U1) are used for USB OSC1 and OSC32K pins ZZG balls P9 and R8 (ZDY balls T2 and U1) are used for USB 200 mV 25 0.8 NOM MAX 2.5 V CVDD UNIT
VI
Input voltage
VID
Differential input voltage
ZZG balls W13, W14, Y12, and Y14 (ZDY balls N9, P11, P10, and T12) are used for CCP 2-mA drive strength buffers
-2 -3 -4 -6 -8 -11 -18.3 2 3 4 6 8 11 18.3 -40 85 C mA mA
Low-voltage range DVDDmin = 1.65 V
3-mA drive strength buffers 4-mA drive strength buffers 6-mA drive strength buffers
PRODUCT PREVIEW
IOH
High-level output current High-voltage range DVDDmin = 2.5 V
8-mA drive strength buffers 11-mA drive strength buffers
18.3-mA drive strength buffers 2-mA drive strength buffers Low-voltage range DVDDmin = 1.65 V Low-level output current High-voltage range DVDDmin = 2.5 V 3-mA drive strength buffers 4-mA drive strength buffers 6-mA drive strength buffers 8-mA drive strength buffers 11-mA drive strength buffers 18.3-mA drive strength buffers TA
IOL
Operating ambient temperature
All core voltage supplies must be tied to the same voltage level (within 50 mV). In Split-power mode (CV DDx and DVDDx = 0), RTC has to be supplied with CVDDRTC = 1.05 V min and DVDDRTC = 1.65 V min. Low-power standby is defined as follows: the device is in deep-sleep mode and LOW_PWR = 1. The device runs from 32-kHz clock in this mode. To filter switching noises, it is recommended that an RC (R = 10 , C = 100 nF) low-pass filter be implemented externally. # Corresponding DV DD mode bit must be configured in the Voltage_control_0 register. || In systems where the CV DDx and DVDDx power supplies are ramped at generally the same time (within 500 ms of one another), there are no specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between CVDD and DVDD is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DVDDx supplies, all DVDDx supplies should be ramped up to valid voltage levels within 500 ms of one another. kAn external capacitor (C = 1 F 10%) must be connected between LDO.FILTER and VSS to provide decoupling capacitance for the regulator. hLDO has to be powered down by setting LDO_PWRDN_CNTL[0] in OMAP5912 configuration.
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5.3
Electrical Characteristics Over Recommended Operating Ambient Temperature Range (Unless Otherwise Noted)
PARAMETER Standard LVCMOS TEST CONDITIONS IO = rated, DVDD = 3.3 V, dual-supply outputs MIN 0.8 DVDD V IO = -18.3 mA IO = rated, DVDD = 3.3 V, dual-supply outputs DVDD - 0.5 TYP MAX UNIT
VOH
High-level output voltage
ZZG balls P9 and R8 (ZDY balls T2 and U1) are not used for USB differential voltage Standard LVCMOS ZZG balls P9 and R8 (ZDY balls T2 and U1) are not used for USB differential voltage I2C
0.22 DVDD
VOL
Low-level output voltage
IO = 18.3 mA Fast mode at 6-mA load Fast mode at 3-mA load Standard mode at 3-mA load Low-voltage range High-voltage range Low-voltage range High-voltage range Low-voltage range High-voltage range Low-voltage range High-voltage range Low-voltage range High-voltage range 0 0 0 -1 -1 5 15 55 35 -20 -60 -170 -110 - 20 ZZG balls P9 and R8 (ZDY balls T2 and U1) (USB) All other I/O pins 7 4 7 4 10 30 100 67 -10 -30 -100 -67
0.28 V 0.6 0.4 0.4
Inputs without internal pullups/pulldowns enabled
VI = VI MAX to VI MIN
1 20 60 170 A 110 -5 -15 -55 -35 20 A pF
Input pins with 20-A pulldowns enabled
DVDD = MAX, VI = VSS to VDD DVDD = MAX, VI = VSS to VDD CVDD = MAX, VI = VSS to VDD CVDD = MAX, VI = VSS to VDD
II
Input current
Input pins with 100-A pulldowns enabled
Input pins with 20-A pullups enabled
Input pins with 100-A pullups enabled IOZ Ci Input current for outputs in high-impedance Input capacitance
Co
Output capacitance
ZZG balls P9 and R8 (ZDY balls T2 and U1) (USB) All other I/O pins
pF
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1
Electrical Specifications
IOL-test
Tester Pin Electronics
50 VLoad CT
Output Under Test
IOH-test
Where:
IOL-test IOH-test VLoad CT
= = = =
5 mA (all outputs) 300 A (all outputs) [(VOH - VOL)/2] + VOL 10 pF maximum and 5 pF minimum for EMIFF (50 pF maximum and 5 pF minimum for EMIFS and all other I/O pads).
Figure 5-1. 3.3-V Test Load Circuit
PRODUCT PREVIEW
5.4
Package Thermal Resistance Characteristics
Table 5-1 provides the thermal resistance characteristics for the recommended package types used on the OMAP5912 device. Table 5-1. Thermal Resistance Characteristics
RJA (C / W) TBD TBD RJC (C / W) TBD TBD Board Type High-K Low-K
Board Types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards For Area Array Surface Mount Package Thermal Measurements.
5.5
Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings: a c d dis en f h r su t v w X access time cycle time (period) delay time disable time enable time fall time hold time rise time setup time transition time valid time pulse duration (width) Unknown, changing, or don't care level Letters and symbols and their meanings: H L V Z High Low Valid High impedance
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Electrical Specifications
5.6
Clock Specifications
This section provides the timing requirements and switching characteristics for the OMAP5912 system clock signals.
5.6.1 32-kHz Oscillator and Input Clock
The 32.768-kHz clock signal (often abbreviated to 32-kHz) may be supplied by either the on-chip 32-kHz oscillator (requiring an external crystal) or an external CMOS signal. The on-chip oscillator requires an external 32.768-kHz crystal connected across the OSC32K_IN and OSC32K_OUT pins. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-2. The load capacitors, C1 and C2, should be chosen such that the equation below is satisfied (recommended values are C1 = C2 = 10 pF). CL in the equation is the load specified for the crystal. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (OSC32K_IN and OSC32K_OUT) and to the VSS pin closest to the oscillator pins (ZZG ball Y13; ZDY ball H8). NOTE 1: Do not connect VSS (ZZG ball Y13; ZDY ball H8) to the common board ground but only to the oscillator circuit as shown. C 1C 2 (C 1 ) C 2)
CL +
OSC32K_IN
VSS (ZZG ball Y13) OSC32K_OUT (ZDY ball H8)
Crystal 32.768 kHz
C1
C2
Do not connect VSS (ZZG ball Y13; ZDY ball H8) to the common board ground but only to the oscillator circuit as shown.
Figure 5-2. 32-kHz Oscillator External Crystal NOTE 2: Recommended maximum series resistance specification of the crystal is 100 k or less at 32 kHz. Series resistance at any other parasitic resonance of the crystal should be greater than 100 k. For crystals whose parasitic resonance has maximum series resistor less than 100 k, a PI-network (Figure 5-3) is needed between the OSC32K_OUT pin and the crystal to suppress oscillation at frequencies other than 32 kHz. The PI-network creates a pole to reduce the negative resistance at frequencies greater than 32 kHz. The recommended PI-network for use with these crystals is CPI = 10 pF total and RPI = 390 k 5%
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Electrical Specifications
OSC32K_IN Crystal 32.768 kHz
VSS (ZZG ball Y13) OSC32K_OUT (ZDY ball H8)
RPI
C1
C2
CPI
Do not connect VSS (ZZG ball Y13; ZDY ball H8) to the common board ground but only to the oscillator circuit as shown.
Figure 5-3. 32-kHz Oscillator External Crystal With PI-Network NOTE 3: When the internal oscillator is used to generate the 32-kHz clock, the CLK32K_IN pin must be tied to VSS. Otherwise, the 32-kHz clock is corrupted and the device fails. If the external CMOS clock is used to provide the 32-kHz clock, the OSC32K_IN (XI) pin must be tied to CVDD. The OSC32K_OUT (XO) pin must be tied to VSS. Table 5-2 shows the switching characteristics of the 32-kHz oscillator and Table 5-3 shows the input requirements of the 32-kHz clock input. Table 5-2. 32-kHz Oscillator Switching Characteristics
PARAMETER Start-up time (from power up until oscillating at stable frequency of 32.768 kHz) IDDA, active current consumption Oscillation frequency TEST CONDITIONS C1 = C2 = 10 pF, CVDD = 1.35 V MIN TYP 200 4 32.768 MAX 800 UNIT ms A kHz
PRODUCT PREVIEW
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Electrical Specifications
Table 5-3. 32-kHz Input Clock Timing Requirements
NO. CK1 CK2 CK3 CK4 CK5 tcyc tf tr Frequency Fall time Rise time Duty cycle (high-to-low ratio) Frequency stability 30 -70 MIN NOM 32.768 25 25 70 70 MAX UNIT kHz ns ns % ppm
CK3 CK2 CK1 CLK32K_IN
Figure 5-4. 32-kHz Input Clock
5.6.2 Base Oscillator (12, 13, or 19.2 MHz) and Input Clock
The internal base system oscillator is enabled following a device reset. The oscillator requires an external crystal to be connected across the OSC1_IN and OSC1_OUT pins. If the internal oscillator is not used (configured in software), an external clock source (12,13, 19.2 MHz) must be applied to the OSC1_IN pin, and the OSC1_OUT pin must be left unconnected. Because the internal oscillator can be used as a clock source to the OMAP DPLL, the 12-,13-, or 19.2-MHz crystal oscillation frequency can be multiplied to generate the DSP clock, MPU clock, traffic controller clock. The crystal must be in fundamental-mode operation, and parallel resonant, with a maximum effective series resistance of 30 maximum. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 5-5. The load capacitors, C1 and C2, must be chosen such that the equation below is satisfied (recommended values are C1 = C2 = 2CL). CL in the equation is the load specified for the crystal. All discrete components used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (OSC1_IN and OSC1_OUT) and to the VSS pins closest to the oscillator pins (ZZG balls AA1 and Y3; ZDY balls G11 and N5). NOTE: The base oscillator is powered by the embedded LDO. If an external clock source is used instead of using the on-chip oscillator, care must be taken that the voltage level driven onto the OSC1_IN pin is no greater than the LDO voltage level. C1 = C2 = 2CL (CL = Crystal Load Capacitance)
OSC1_IN
OSC1_OUT
12, 13, or 19.2-MHz Crystal
C1
C2
Figure 5-5. Internal System Oscillator External Crystal
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PRODUCT PREVIEW
Electrical Specifications
If USB host function is used, it is recommended that a very low PPM crystal ( 50 ppm) be used for the 12,13, or 19.2 MHz oscillator circuit. If the USB host function is not used, then a crystal of 180 ppm is recommended. When selecting a crystal, the system design must take into account the temperature and aging characteristics of a crystal versus the user environment and expected lifetime of the system. Table 5-4 shows the switching characteristics of the base oscillator. Table 5-4. Base Oscillator Switching Characteristics
PARAMETER Start-up time (from power up until oscillating at stable frequency of 12,13, or 19.2 MHz) IDDA, active current consumption Oscillation frequency TEST CONDITIONS C1 = C2 = 10 pF, CVDD = 1.3V C1 = C2 = 10 pF, CVDD = 1.5V MIN TYP 1.7 220 12 to 19.2 MAX 3 UNIT ms A MHz
PRODUCT PREVIEW
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Electrical Specifications
5.7
Reset Timings
This section provides the timing requirements for the OMAP5912 hardware reset signals.
5.7.1 OMAP5912 Device Reset
The PWRON_RESET signal is the active-low asynchronous reset input responsible for the reset of the entire OMAP5912 device. When using an external crystal to supply the 32-kHz system clock, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles longer than the worst-case start-up time of the 32-kHz oscillator after stable power supplies (see Figure 5-6). If an external CMOS input signal is used to source 32 kHz, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles after stable power supplies. See Table 5-5 and Table 5-6. Table 5-5. OMAP5912 Device Reset Timing Requirements
NO. RS1 tw(PWRON_RST) Pulse duration, PWRON_RESET low MIN 800 MAX UNIT ms
Table 5-6. OMAP5912 Device Reset Switching Characteristics
NO. RS2
PARAMETER td(PWRONH-RSTH) Delay time, PWRON_RESET high to RST_OUT high
MIN
MAX T + 10
UNIT s
T = P*(C + 7), P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh)
CVDDx
DVDDx
2 Cycles Worst-case Oscillator Start-up Time OSC32K_IN RS1 PWRON_RESET RS2 RST_OUT
Figure 5-6. Device Reset Timings
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PRODUCT PREVIEW
Electrical Specifications
5.7.2 OMAP5912 MPU Core Reset
The MPU_RST signal is the active-low asynchronous input responsible for the reset of the OMAP5912 MPU core. Stable power supplies are assumed prior to MPU_RST assertion. Figure 5-7 illustrates the behavior of MPU_RST and RST_OUT. In Figure 5-7, a logic-high level is assumed on the PWRON_RESET input. In the case where an application ties the PWRON_RESET and MPU_RST together, the behavior described in Section 5.7.1, OMAP5912 Device Reset, will override. See Table 5-7 and Table 5-8. Table 5-7. MPU_RST Timing Requirements
NO. M3 tw(MPU_RST) Pulse duration, MPU_RST low MIN 50 MAX UNIT s
Table 5-8. MPU_RST Switching Characteristics
NO. M1 td(MPUL-RSTL) PARAMETER Delay time, MPU_RST low to RST_OUT low MPU_RST asserted during OMAP5912 awake state MIN MAX 1 10 s T + 10 UNIT s
PRODUCT PREVIEW
M2
td(MPUH-RSTH)
Delay time, MPU_RST high to RST_OUT high
MPU_RST asserted during OMAP5912 deep-sleep state
T = P*(C + 7), P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh)
M3 MPU_RST M1 RST_OUT M2
Figure 5-7. MPU Core Reset Timings
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Electrical Specifications
5.8
External Memory Interface Timing
Some EMIFF and EMIFS output terminals have the following particularity: A serial resistor of 20 is included at the output of the terminal to match with PCB line impedance and ensure proper signal integrity. See Table 2-3 (ZDY Package Terminal Characteristics) and Table 2-4 (ZZG Package Terminal Characteristics) for the list of terminals, which are concerned.
GZ HHV R 20 W Y PAD
A MODE
5.8.1 EMIFS/Flash Interface Timing
Table 5-9 and Table 5-10 assume testing over recommended operating conditions (see Figure 5-8 through Figure 5-12). Table 5-9. EMIFS/Flash Interface Timing Requirements
NO. Async modes (RT = 0) Sync Modes (RT = 1) Async modes (RT = 0) Sync Modes (RT = 1) Async modes (RT = Sync modes (RT = 0) DVDD5 = 1.8 V Nominal MIN F6 F7 tsu(RDV-CLKH) th(CLKH-RDV) Setup time, read data valid before FLASH.CLK high Hold time, read data valid after FLASH.CLK high Setup time, FLASH.RDY valid before FLASH.CLK high Hold time, FLASH.RDY valid after FLASH.CLK high 2 2 4 3 7 2 0,5 3 MAX DVDD5 = 2.75 V Nominal MIN 2 2 4 3 7 2 0,5 3 MAX DVDD5 = 3.3 V Nominal MIN 2 2 4 3 7 2 0,5 3 MAX ns ns ns ns ns ns ns ns UNIT
F10
tsu(RDY-CLKH)
1)
Async modes (RT = 0) Sync modes (RT = 1)
F11
th CLKH RDY h(CLKH-RDY)
When the RT field in the EMIFS configuration register is set, input data is retimed to the external FLASH.CLK signal. RT=1 setting is only valid in synchronous modes (protocols 1 and 2). For asynchronous modes, td(CLKH-CSV) with respect to internal FLASH.CLK is given as 0 to allow for other signals reference to FLASH.CSx. The external FLASH.CLK is disabled for async modes
The EMIFS/Flash Clock is limited by the maximum traffic controller clock rate for OMAP5912, provided that all EMIFS/Flash timing constraints are met. Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V.
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Electrical Specifications
Table 5-10. EMIFS/NOR Flash Interface Switching Characteristics
NO.
PARAMETER async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes
DVDD5 = 1.8 V Nominal MIN MAX 19 9.5 14.5 5 3.5 1.5 18.5 9 2 0 2 0 3 1 3 11.5 2 14 4.5 13.5 10 2 10 6 1 + 0.5P 4 + 05.P
DVDD5 = 2.75 V Nominal MIN 2.5 0 MAX 17 8.5 12.5 4.5 3.5 1.5 16.5 8.5 2.5 0 2.5 0.5 3 1 3.5 9.5 1 12 4 12 9 2 9 4.5 1 + 0.5P 3.5 + 0.5P
DVDD5 = 3.3 V Nominal MIN 2.5 0 MAX 16
UNIT
F1
td(CLKH-CSV)
Delay time, FLASH.CLK high to FLASH.CSx transition Delay time, FLASH.CLK high to FLASH.BEx valid Delay time, FLASH.CLK high to FLASH.BEx invalid Delay time, FLASH.CLK high to address valid
2 0
ns 8.5 11.5 ns 4 3.5 ns 1.5 15.5 ns 8 2.5 ns 0 2.5 0 3 1 3 8.5 ns 1 11 ns 3.5 11 8 2 8.5 4.5 1 + 0.5P 3.5 + 0.5P ns ns ns ns ns ns
F2
td(CLKH-BEV)
F3
td(CLKH-BEIV)
PRODUCT PREVIEW
F4
td(CLKH-AV)
F5
td(CLKH-AIV)
Delay time, FLASH.CLK high to address invalid Delay time, FLASH.CLK high to FLASH.ADV transition Delay time, FLASH.CLK high to FLASH.OE transition
F8
td(CLKH-ADV)
F9
td(CLKH-OEV)
F12 F13 F14 F15 F16 F17
td(CLKH-WEV) td(CLKH-WDV) td(CLKH-WDIV) td(CLKH-DHZ) td(CLKH-DLZ) td(CLKH-BAAV)
Delay time, FLASH.CLK high to FLASH.WE transition Delay time, FLASH.CLK high to write data valid Delay time, FLASH.CLK high to write data invalid Delay time, FLASH.CLK high to data bus high-impedance Delay time, FLASH.CLK high to data bus driven Delay time, FLASH.CLK high to FLASH.BAA transition
The EMIFS/flash clock rate can be limited only by the maximum traffic controller clock rate for the OMAP5912, provided all EMIFS/flash timing constraints are met. Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. Data is referenced to the internal FLASH.CLK. P = period of undivided traffic controller clock regardless of FLASH.CLK divider configuration.
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Electrical Specifications
N Cycles M Cycles FLASH.CLK (Internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[25:1] A1 F6 FLASH.D[15:0] F8 FLASH.ADV F9 FLASH.OE F9 F8 D1 F7 Valid F5 F3 F1
FLASH.WE F10 FLASH.RDY
F11
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers.
Figure 5-8. EMIFS/NOR Flash - Asynchronous Memory Read Timing
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Electrical Specifications
N Cycles M Cycles FLASH.CLK (Internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F8 FLASH.ADV F4 FLASH.A[25:1] Valid Address 0 F6 FLASH.D[15:0] F9 FLASH.OE D1 Upper F9 F7 F5 Valid Address 1 F6 D1 Lower F7 Valid F8 F3 F1 N Cycles M Cycles
PRODUCT PREVIEW
FLASH.WE
FLASH.RDY
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. Although shown as always high in this timing diagram, FLASH.RDY may be used to insert wait-states at any time during the cycle.
Figure 5-9. EMIFS/NOR Flash - Asynchronous 32-Bit Read
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Electrical Specifications
M Cycles M Cycles M Cycles M Cycles
M Cycles N Cycles FLASH.CLK (Internal) F1 FLASH.CSx F2 FLASH.BE[1:0] F8 FLASH.ADV F4 F5 Add1 Add0 F6 FLASH.D[15:0] F9 FLASH.OE D0 D1 D2
M Cycles N Cycles
F1
F3 Valid F8
F4 Add2 Add3 Add4 F7 D3 D4 D5 D6 D7 Add5 Add6 Add7
F5
FLASH.A[25:1]
F9
FLASH.WE
FLASH.RDY
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers. Although shown as always high in this timing diagram, FLASH.RDY may be used to insert wait-states at any time during the cycle.
Figure 5-10. EMIFS/NOR Flash - Asynchronous Read - Page Mode 8 x 16 Bit
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PRODUCT PREVIEW
Electrical Specifications
ADV width N Cycles FLASH.CLK (Internal) FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[25:1] F13 F16 FLASH.D[15:0] F8 F8 FLASH.ADV D1 A1 F15 F14 Valid F5 F3 Wait-states M Cycles WE width P Cycles CS hold Q Cycles
F1
F1
PRODUCT PREVIEW
FLASH.OE F12 FLASH.WE F11 F10 FLASH.RDY
F12
F10
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers.
Figure 5-11. EMIFS/NOR Flash - Asynchronous Memory Write Timing
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Electrical Specifications
M Cycles Wait-States N Cycles
CLK Start Q Cycles FLASH.CLK (External) F1 FLASH.CSx F2 FLASH.BE[1:0] F4 FLASH.A[25:1]
F1
F3 Valid F5 A1 F6 F7 F6 D2 D3 D4 D5 D6 D7 F7 D1
FLASH.D[15:0] F8 FLASH.ADV F8
D0
F7 FLASH.BAA F9 FLASH.OE
F17
F9
FLASH.WE
FLASH.RDY

FLASH.CLK is only driven during the active portion of the cycle. For reference, the dashed line shows FLASH.CLK as if it were continuous. Number of cycles is configurable via EMIFS setup registers. Although shown as always high in this timing diagram, FLASH.RDY may be used to insert wait-states at any time during the cycle.
Figure 5-12. EMIFS/NOR Flash - Synchronous Burst Read
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PRODUCT PREVIEW
Electrical Specifications
5.8.2 EMIFS/Multiplexed NOR Flash Interface Timings
Table 5-11 and Table 5-12 assume testing over recommended operating conditions (see Figure 5-13 through Figure 5-15). Table 5-11. EMIFS/Mux NOR Flash Interface Timing Requirements
NO. Async modes (RT = 0) Sync modes (RT = 1) Async modes (RT = 0) Sync modes (RT = 1) Async modes (RT = 0) Sync modes (RT = 1) Async modes (RT = 0) Sync modes (RT = 1) DVDD5 = 1.8 V Nominal MIN Setup time, input data valid before FLASH.CLK high 2 2 4 3 7 2 0.5 3 MAX DVDD5= 2.75 V Nominal MIN 2 2 4 3 7 2 0.5 3 MAX DVDD5 = 3.3 V Nominal MIN 2 ns 2 4 ns 3 7 ns 2 0.5 ns 3 MAX UNIT
MF8
tsu(DV-CLKH)
MF9
th(CLKH-DV)
Hold time, input data valid after FLASH.CLK high
MF10
PRODUCT PREVIEW
tsu(RDYV-CLKH)
Setup time, FLASH.RDY valid before FLASH.CLK high
MF11
th(CLKH-RDYV)
Hold time, FLASH.RDY valid after FLASH.CLK high
The EMIFS/flash clock rate can be limited only by the maximum traffic controller clock rate for the OMAP5912, provided all EMIFS/flash timing constraints are met. Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. When the RT field in the EMIFS configuration register is set, input data is retimed to the external FLASH.CLK signal. The RT = 1 setting is only valid in synchronous modes (protocols 1 and 2). The RT = 0 setting in synchronous modes is ensured only for traffic controller clock frequencies of 50 MHz and lower.
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Electrical Specifications
Table 5-12. EMIFS/MUX NOR Flash Interface Switching Characteristics
NO. PARAMETER async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes async modes sync modes 2.5 0 3 13.5 10 2 2 2 0 10.5 0.5 2.5 0 3.5 12 9 2 DVDD5 = 1.8 V Nominal MIN 2 0 2 0 3 1 Delay time, FLASH.CLK high to FLASH.CSx transition MAX 19 9.5 11.5 2 14 4.5 11 1.5 2.5 0 9 0.5 2.5 ns 0 3 11 8 ns ns ns DVDD5 = 2.75 V Nominal MIN 2.5 0 2.5 0.5 3 1 MAX 17 8.5 9.5 1 12 4 9.5 1 2.5 ns 0 8.5 ns 0.5 DVDD5 = 3.3 V Nominal MIN 2.5 0 2.5 0 3 1 MAX 16 ns 8.5 8.5 ns 1 11 ns 3.5 8.5 ns UNIT
MF1
td(CLKH-CSV)
MF2
td(CLKH-ADV)
Delay time, FLASH.CLK high to FLASH.ADV transition
MF3
td(CLKH-OEV)
Delay time, FLASH.CLK high to FLASH.OE transition
MF4
td(CLKH-AV)
MF5
td(CLKH-AIV)
Delay time, FLASH.CLK high to address invalid (FLASH.A[25:17])
MF6
td(CLKH-DAV)
Delay time, FLASH.CLK high to address valid (FLASH.A[16:1].D[15:0])
MF7
td(CLKH-DAIV)
Delay time, FLASH.CLK high to address invalid (FLASH.A[16:1].D[15:0])
MF12 MF13 MF14
td(CLKH-WEV) td(CLKH-DV) td(CLKH-DIV)
Delay time, FLASH.CLK high to FLASH.WE transition Delay time, FLASH.CLK high to write data valid Delay time, FLASH.CLK high to write data invalid
The EMIFS/flash clock rate can be limited only by the maximum traffic controller clock rate for the OMAP5912, provided all EMIFS/flash timing constraints are met. Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. Data is referenced to the internal FLASH.CLK.
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PRODUCT PREVIEW
Delay time, FLASH.CLK high to address valid (FLASH.A[25:17])
0.5
Electrical Specifications
ADV Width M Cycles FLASH.CLK (Internal) MF1 FLASH.CSx MF2 FLASH.ADV MF2
N Cycles
MF1
MF3 FLASH.OE MF4 FLASH.A[25:17] Address (MSB) MF8 MF6 FLASH.A[16:1] .D[15:0] FLASH.RDY
MF3
MF5
MF7 Address (LSB) MF10 MF11
MF9 DIN
PRODUCT PREVIEW
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers.
Figure 5-13. EMIFS/MUX NOR Flash - Single Word Asynchronous Read
ADV Width N Cycles FLASH.CLK (Internal) MF1 FLASH.CSx MF2 FLASH.ADV FLASH.OE MF2
Wait States M Cycles
WE Width P Cycles
WE Width P Cycles
MF1
MF12 FLASH.WE MF4 FLASH.A[25:17] Address (MSB) MF6 FLASH.A[16:1] .D[15:0] FLASH.RDY
MF12
MF5
MF7
MF13 DOUT MF10 MF11
MF14
Address (LSB)
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. Number of cycles is configurable via EMIFS setup registers.
Figure 5-14. EMIFS/MUX NOR Flash - Single Word Asynchronous Write
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Electrical Specifications
ADV Width N Cycles M Cycles
CLK Start Q Cycles FLASH.CLK (External) MF1 FLASH.CSx MF2 MF2 FLASH.ADV
MF1
MF3 FLASH.OE MF4 FLASH.A[25:17] Address (MSB) MF6 FLASH.A[16:1] .D[15:0] FLASH.RDY

MF3
MF5
MF7 Address (LSB)
DIN 0 DIN 1
MF8
DIN 7
MF9
FLASH.CLK is only driven during the active portion of the cycle. For reference, the dashed line shows FLASH.CLK as if it were continuous. Number of cycles is configurable via EMIFS setup registers. Although shown as always high in this timing diagram, FLASH. RDY may be used to insert wait-states at any time during the cycle.
Figure 5-15. EMIFS/MUX NOR Flash - Synchronous Four-Word Burst Read
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PRODUCT PREVIEW
Electrical Specifications
5.8.3 EMIFS/NAND Flash Timings
Table 5-13 and Table 5-14 assume testing over operating conditions (see Figure 5-16 through Figure 5-19). Table 5-13. EMIFS/NAND Flash Timing Requirements
NO. Setup time, input FLASH.D[15:0] valid before FLASH.CLK high Hold time, input FLASH.D[15:0] valid after FLASH.CLK high DVDD5 = 1.8 V Nominal MIN NFE10 NFE11
DVDD5 = 2.75 V Nominal MIN 2 3 MAX
DVDD5 = 3.3 V Nominal MIN 2 3 MAX
UNIT
MAX
tsu(DV-CLKH) th(CLKH-DV)
2 3
ns ns
Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V.
Table 5-14. EMIFS/NAND Flash Switching Characteristics
NO. PARAMETER Delay time, FLASH.CLK high to FLASH.A[1] (CLE) valid Delay time, FLASH.CLK high to FLASH.A[1] (CLE) invalid Delay time, FLASH.CLK high to FLASH.CS2U (CE) transition Delay time, FLASH.CLK high to FLASH.CS2UWE (WE) transition Delay time, FLASH.CLK high to FLASH.A[2] (ALE) valid Delay time, FLASH.CLK high to FLASH.A[2] (ALE) invalid Delay time, FLASH.CLK high to FLASH.D[15:0] valid Delay time, FLASH.CLK high to FLASH.D[15:0] invalid Delay time, FLASH.CLK high to FLASH.CS2UOE (RE) transition 2 14.5 3 10 2 14.5 3 3.5 14.5 13.5 13 3.5 9 2 14.5 3 DVDD5 = 1.8 V Nominal MIN MAX 13.5 3.5 14.5 12 11.5 3.5 8 3 DVDD5 = 2.75 V Nominal MIN MAX 12 3.5 14.5 11 10 DVDD5 = 3.3 V Nominal MIN MAX 11 ns ns ns ns ns ns ns ns ns UNIT
PRODUCT PREVIEW
NFE1 NFE2 NFE3 NFE4 NFE5 NFE6 NFE7 NFE8 NFE9
td(CLKH-CLEV) td(CLKH-CLEIV) td(CLKH-CEV) td(CLKH-WEV) td(CLKH-ALEV) td(CLKH-ALEIV) td(CLKH-DV) td(CLKH-DIV) td(CLKH-REV)
Timing values are given for the CONF_VOLTAGE_FLASH_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V.
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SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
FLASH.CLK (Internal) NFE1 FLASH.A[1] (CLE) NFE3 FLASH.CS2U (CE) NFE4 FLASH.CS2UWE (WE) NFE5 FLASH.A[2] (ALE) NFE7 FLASH.D[15:0] (I/O) Command NFE8 NFE6 NFE4 NFE3 NFE2
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. When a NAND CE care Flash type is used, FLASH.CS2U is a combination of a GPIO (controlled by software--no timing) and CS2U (internal).
Figure 5-16. EMIFS/NAND Flash - Command Latch Timing
FLASH.CLK (Internal) NFE1 FLASH.A[1] (CLE) NFE3 FLASH.CS2U (CE) NFE4 FLASH.CS2UWE (WE) NFE5 FLASH.A[2] (ALE) NFE7 FLASH.D[15:0] (I/O)
Col. Add1 Col. Add2
NFE4
NFE6
NFE8
Row Add1 Row Add2
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. When a NAND CE care Flash type is used, FLASH.CS2U is a combination of a GPIO (controlled by software--no timing) and CS2U (internal).
Figure 5-17. EMIFS/NAND Flash - Address Latch Timing
December 2003 - Revised March 2004
SPRS231B
195
PRODUCT PREVIEW
Electrical Specifications
FLASH.CLK (Internal) NFE2 FLASH.A[1] (CLE) NFE3 FLASH.CS2U (CE) NFE5 FLASH.A[2] (ALE) NFE4 FLASH.CS2UWE (WE) NFE7 FLASH.D[15:0] (I/O)
NFE4
NFE8 DOUT 1 DOUT N
DOUT 0
PRODUCT PREVIEW
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. When a NAND CE care Flash type is used, FLASH.CS2U is a combination of a GPIO (controlled by software--no timing) and CS2U (internal).
Figure 5-18. EMIFS/NAND Flash - Memory Write Timing
196
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
FLASH.CLK (Internal) NFE1 FLASH.A[1] (CLE) NFE3 FLASH.CS2U (CE) NFE4 FLASH.CS2UWE (WE) NFE5 FLASH.A[2] (ALE) NFE9 FLASH.CS2UOE (RE) NFE10 FLASH.D[15:0] (I/O) FLASH.RDY (R/B)
NFE9
NFE11 DIN N + 1 DIN M
DIN N
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to express relative timings. When a NAND CE care Flash type is used, FLASH.CS2U is a combination of a GPIO (controlled by software--no timing) and CS2U (internal). The flash Ready/Busy input is monitored by software.
Figure 5-19. EMIFS/NAND Flash - Memory Read Timing
December 2003 - Revised March 2004
SPRS231B
197
PRODUCT PREVIEW
Electrical Specifications
5.9
CompactFlash Interface Timings
Table 5-15 and Table 5-16 assume testing over operating conditions (see Figure 5-20 through Figure 5-25). Table 5-15. CompactFlash Interface Timing Requirements
NO. Setup time, FLASH.D[15:0] valid before internal clock high Hold time, FLASH.D[15:0] valid after internal clock high Setup time, FLASH.RDY valid before internal clock high Hold time, FLASH.RDY valid after internal clock high
DVDD5 = 1.8 V Nominal MIN MAX
DVDD5 = 2.75 V Nominal MIN 2 3 2 3 MAX
DVDD5 = 3.3 V Nominal MIN 2 3 2 3 MAX
UNIT
CF5 CF6 CF9 CF10
tsu(DV-CLKH) th(DV-CLKH) tsu(RDYV-CLKH) th(CLKH-RDYV)
2 3 2 3
ns ns ns ns
Table 5-16. CompactFlash Interface Switching Characteristics
PRODUCT PREVIEW
NO.
PARAMETER Delay time, internal clock to Address (FLASH.A[10:1] and A[14]) transition Delay time, internal clock to REG (FLASH.A[13]) transition Delay time, internal clock to CS (FLASH.BEx) transition Delay time, internal clock to OE (FLASH.OE) transition Delay time, internal clock to WE (FLASH.WE) transition Delay time, internal clock to data (FLASH.D[15:0]) valid Delay time, internal clock to IORD (FLASH.A[11]) transition Delay time, internal clock to IOS16 (CFLASH.IOSIS16) transition Delay time, internal clock to IOWR (FLASH.A[12]) transition
DVDD5 = 1.8 V Nominal MIN MAX 9 9 1.5 1 3 4.5 13.5 10 9 1.5 4 9
DVDD5 = 2.75 V Nominal MIN MAX 8.5 8.5 1.5 1 3.5 4 12 9 8.5 1.5 4 8.5
DVDD5 = 3.3 V Nominal MIN MAX 8 8 1.5 1 3 3.5 11 8 8 1.5 4 8
UNIT
CF1 CF2 CF3 CF4 CF7 CF8 CF11 CF12 CF13
td(CLKH-AV) td(CLKH-REGV) td(CLKH-CSV) td(CLKH-OEV) td(CLKH-WEV) td(CLKH-DV) td(CLKH-IORDV) td(CLKH-IOIS16V) td(CLKH-IOWRV)
ns ns ns ns ns ns ns ns ns
198
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF4 FLASH.OE (OE) CF5 CF6 FLASH.D[15:0] (I/O)
CF1
CF2
CF3
CF4
DIN
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-20. CompactFlash - Attribute Memory Mode Read Timing
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF7 FLASH.WE (WE) CF7 CF3 CF2 CF1
FLASH.OE (OE) CF8 FLASH.D[15:0] (I/O) DIN CF8
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-21. CompactFlash - Attribute Memory Mode Write Timing
December 2003 - Revised March 2004
SPRS231B
199
PRODUCT PREVIEW
Electrical Specifications
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF4 FLASH.OE (OE) CF9 CF10 CF4 CF3 CF2 CF1
PRODUCT PREVIEW
FLASH.RDY (WAIT) CF5 CF6 FLASH.D[15:0] (I/O) DIN
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-22. CompactFlash - Common Memory Mode Read Timing
200
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF7 FLASH.WE (WE) CF9 CF10 FLASH.RDY (WAIT) CF8 CF8 FLASH.D[15:0] (I/O) DOUT CF7 CF3 CF2 CF1
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-23. CompactFlash - Common Memory Mode Write Timing
December 2003 - Revised March 2004
SPRS231B
201
PRODUCT PREVIEW
Electrical Specifications
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF11 FLASH.A[11] (IORD) CF12 CFLASH.IOIS16 (IOIS16) CF12 CF11 CF3 CF2 CF1
PRODUCT PREVIEW
CF9 CF10 FLASH.RDY (WAIT) CF5 CF6 FLASH.D[15:0] (I/O) DIN
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-24. CompactFlash - I/O Mode Read Timing
202
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Internal Clock CF1 FLASH.A[10:1] FLASH.A[14] (A[10:0]) CF2 FLASH.A[13] (REG) CF3 FLASH.BEx (CE) CF13 FLASH.A[12] (IOWR) CF12 CFLASH.IOIS16 (IOIS16) CF9 CF10 FLASH.RDY (WAIT) CF8 FLASH.D[15:0] (I/O) DOUT CF8 CF12 CF13 CF3 CF2 CF1
The signal shown represents the internal clock signal given as a reference to express relative timings.
Figure 5-25. CompactFlash - I/O Mode Write Timing
December 2003 - Revised March 2004
SPRS231B
203
PRODUCT PREVIEW
Electrical Specifications
5.10 EMIFF/SDR SDRAM Interface Timing
Table 5-17 and Table 5-18 assume testing over operating conditions (see Figure 5-26 through Figure 5-31). Table 5-17. EMIFF/SDR SDRAM Interface Timing Requirements
NO. Setup time, read data valid before SDRAM.CLK high Hold time, read data valid after SDRAM.CLK high DVDD4 = 1.8 V Nominal MIN SD7 SD8
DVDD4 = 2.75 V Nominal MIN 2 1.5 MAX
DVDD4 = 3.3 V Nominal MIN 2 1.5 MAX
UNIT
MAX
tsu(DV-CLKH) th(CLKH-DV)
2 1.5
ns ns
Timing is ensured up to the maximum EMIFF/SDRAM clock rate when the SD_RET field in the EMIFF configuration register is set. Timing is ensured independent of SD_REF for EMIFF/SDRAM clock rates of 50 MHz and lower. Timing values are given for the CONF_VOLTAGE_SDRAM_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V.
Table 5-18. EMIFF/SDR SDRAM Interface Switching Characteristics
NO. PARAMETER tc(CLK) tw(CLK) td(CLKH-DQMV) td(CLKH-DQMIV) td(CLKH-AV) td(CLKH-AIV) td(CLKH-SDCASL) td(CLKH-SDCASH) td(CLKH-DV) td(CLKH-DIV) td(CLKH-SDWEL) td(CLKH-SDWEH) td(CLKH-BAV) td(CLKH-BAIV) td(CLKH-RASL) td(CLKH-RASH) Cycle time, SDRAM.CLK Pulse duration, SDRAM.CLK high/low Delay time, SDRAM.CLK high to SDRAM.DQMx valid Delay time, SDRAM.CLK high to SDRAM.DQMx invalid Delay time, SDRAM.CLK high to SDRAM.A[13:0] address valid Delay time, SDRAM.CLK high to SDRAM.A[13:0] address invalid Delay time, SDRAM.CLK high to SDRAM.CAS low Delay time, SDRAM.CLK high to SDRAM.CAS high Delay time, SDRAM.CLK high to SDRAM.D[15:0] data valid Delay time, SDRAM.CLK high to SDRAM.D[15:0] data invalid Delay time, SDRAM.CLK high to SDRAM.WE low Delay time, SDRAM.CLK high to SDRAM.WE high Delay time, SDRAM.CLK high to SDRAM.BA[1:0] valid Delay time, SDRAM.CLK high to SDRAM.BA[1:0] invalid Delay time, SDRAM.CLK high to SDRAM.RAS low Delay time, SDRAM.CLK high to SDRAM.RAS high DVDD4 = 1.8 V Nominal MIN SD1 SD2 SD3 SD4 SD5 SD6 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18
DVDD4 = 2.75 V Nominal MIN 10 4.5 MAX
DVDD4 = 3.3 V Nominal MIN 10 4.5 MAX
UNIT ns ns
PRODUCT PREVIEW
MAX
10 4.5 2 2 3 3 3 3 2 2 3 3 3 3 3 3 8 8 7 7 7 7 8 8 7 7 7 7 7 7
2 2 3 3 3 3 2 2 3 3 3 3 3 3
8 8 7 7 7 7 8 8 7 7 7 7 7 7
2 2 3 3 3 3 2 2 3 3 3 3 3 3
8 8 7 7 7 7 8 8 7 7 7 7 7 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Timing is ensured up to the maximum EMIFF/SDRAM clock rate when the SD_RET field in the EMIFF configuration register is set. Timing is ensured independent of SD_REF for EMIFF/SDRAM clock rates of 50 MHz and lower. Timing values are given for the CONF_VOLTAGE_SDRAM_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. The maximum EMIFF/SDRAM clock rate is limited to the maximum traffic controller clock rate for the OMAP5912.
204
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
READ SDRAM.CLK SD2 SDRAM.CKE SD3 SDRAM.DQMx SD5 SDRAM.A[13:0] CA1 SD15 SDRAM.BA[1:0] Bank Address SD7 SDRAM.D[15:0] SDRAM.RAS SD9 SDRAM.CAS SD10 D1 SD8 D2 SD6 CA2 SD16 SD1 SD2 READ
SDRAM.WE
Figure 5-26. EMIFF/SDR Two SDRAM RD (Read) Commands (Active Row)
WRITE SDRAM.CLK
WRITE
SDRAM.CKE SD3 SDRAM.DQMx SD5 SDRAM.A[13:0] SD15 SDRAM.BA[1:0] SD11 SDRAM.D[15:0] D1 Bank Address SD12 D2 CA1 BE1 SD6 CA2 SD16 SD4 BE2
SDRAM.RAS SD9 SDRAM.CAS SD13 SDRAM.WE SD14 SD10
Figure 5-27. EMIFF/SDR Two SDRAM WRT (Write) Commands (Active Row)
December 2003 - Revised March 2004
SPRS231B
205
PRODUCT PREVIEW
Electrical Specifications
ACTV SDRAM.CLK
SDRAM.CKE SDRAM.DQMx SD5 SDRAM.A[13:0] SD15 SDRAM.BA[1:0] SDRAM.D[15:0] SD17 SDRAM.RAS SDRAM.CAS SD18 Bank Activate Row Address
PRODUCT PREVIEW
SDRAM.WE
Figure 5-28. EMIFF/SDR SDRAM ACTV (Active Row) Command
DCAB SDRAM.CLK SDRAM.CKE SDRAM.DQMx SDRAM.A[13:11, 9:0] SDRAM.BA[1:0] SDRAM.D[15:0] SD5 SDRAM.A[10] SD17 SDRAM.RAS SDRAM.CAS SD13 SDRAM.WE SD14 SD18 SD6
Figure 5-29. EMIFF/SDR SDRAM DCAB (Precharge/Deactivate Row) Command
206
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
REFR SDRAM.CLK SDRAM.CKE SDRAM.DQMx SDRAM.A[13:11, 9:0] SDRAM.BAx SDRAM.D[15:0] SD5 SDRAM.A[10] SD17 SDRAM.RAS SD9 SDRAM.CAS SDRAM.WE SD10 SD18 SD6
Figure 5-30. EMIFF/SDR SDRAM REFR (Refresh) Command
MRS SDRAM.CLK
SDRAM.CKE SDRAM.DQMx SD5 SDRAM.A[13:11,9:0] MRS Value SD6
SDRAM.BA[1:0]
SDRAM.D[15:0] SD5 SDRAM.A10 SD17 SDRAM.RAS SD9 SDRAM.CAS SD13 SDRAM.WE SD14 SD10 SD18 SD6
Figure 5-31. EMIFF/SDR SDRAM MRS (Mode Register Set) Command
December 2003 - Revised March 2004
SPRS231B
207
PRODUCT PREVIEW
Electrical Specifications
5.11 EMIFF/DDR SDRAM Interface Timing
Table 5-19 and Table 5-20 assume testing over operating conditions (see Figure 5-32 through Figure 5-34). Table 5-19. EMIFF/DDR SDRAM Interface Timing Requirements
NO. DLL phase = 72 DLL phase = 90 DLL phase = 72 DLL phase = 90 DVDD4 = 1.8 V Nominal MIN Delay time, SDRAM.DQSL/H input high to SDRAM.D[15:0] input data valid -0.2P MAX 0.2P - 0.8 DVDD4 = 2.75 V Nominal MIN -0.2P MAX 0.2P - 0.8 DVDD4 = 3.3 V Nominal MIN -0.2P MAX 0.2P - 0.8 ns -0.25P 0.25P - 0.8 -0.25P 0.25P - 0.8 -0.25P 0.25P - 0.8 UNIT
DD12
td(DQSL/MH-DV)
DD13
td(DQSL/ML-DV)
Delay time, SDRAM.DQSL/H input low to SDRAM.D[15:0] input data valid
-0.2P
0.2P - 0.8
-0.2P
0.2P - 0.8
-0.2P
0.2P - 0.8 ns
-0.25P
0.25P - 0.8
-0.25P
0.25P - 0.8
-0.25P
0.25P - 0.8
PRODUCT PREVIEW
Timing values are given for the CONF_VOLTAGE_SDRAM_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. Delay time assumes that WRITE_OFFSET bits value = 0 (in the DLL_URD_CONTROL and DLL_LRD_CONTROL registers). P = SDRAM.CLK (CLKX) period. Delay time assumes that WRITE_OFFSET bits value = 0 (in the DLL_URD_CONTROL and DLL_LRD_CONTROL registers). Defined in the EMIFF DLL Read Control Register (DLL_PHASE bit).
208
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Table 5-20. EMIFF/DDR SDRAM Interface Switching Characteristics
DVDD4 = 1.8 V Nominal MIN DD1 DD2 DD3 tc(CLK) tw(CLK) td(CLKH-CSV) td(CLKH-CAS/RASL) Cycle time, SDRAM.CLK (CLKX) Pulse duration, SDRAM.CLK (CLKX) high/low Delay time, SDRAM.CLK high to SDRAM.CS transition Delay time, SDRAM.CLK high to SDRAM.CAS/ SDRAM.RAS low Delay time, SDRAM.CLK high to SDRAM.CAS/ SDRAM.RAS high Delay time, SDRAM.CLK high to SDRAM.BA[1:0] valid Delay time, SDRAM.CLK high to SDRAM.BA[1:0] invalid Delay time, SDRAM.CLK high to SDRAM.A[13:0] valid Delay time, SDRAM.CLK high to SDRAM.A[13:0] invalid Delay time, SDRAM.CLK high to SDRAM.WE low Delay time, SDRAM.CLK high to SDRAM.WE high Delay time, SDRAM.DQSL/H high to SDRAM.D[15:0] data valid DLL phase = 72 DLL phase = 90 DLL phase = 72 DLL phase = 90 1.3 10 4.5 3 7 MAX DVDD4 = 2.75 V Nominal MIN 10 4.5 3 7 MAX DVDD4 = 3.3 V Nominal MIN 10 4.5 3 7 MAX ns ns ns
NO.
PARAMETER
UNIT
DD4
3
7
3
7
3
7
ns
DD5
td(CLKH-CAS/RASH) td(CLKH-BAV) td(CLKH-BAIV) td(CLKH-AV) td(CLKH-AIV) td(CLKH-WEL) td(CLKH-WEH)
3
7
3
7
3
7
ns
DD6
3
7
3
7
3
7
ns
DD7
3
7
3
7
3
7
ns
DD8
3
7
3
7
3
7
ns
DD9
3
7
3
7
3
7
ns
DD10 DD11
3 3
7 7 0.2P + 1
3 3
7 7 0.2P + 1
3 3
7 7 0.2P + 1
ns ns
DD14
td(DQSL/HH-DV)
ns 0.25P + 1 0.25P + 1 0.25P + 1
DD15
td(DQSL/HL-DV)
Delay time, SDRAM.DQSL/H low to SDRAM.D[15:0] data valid
0.2P + 0.8
0.2P + 0.8
0.2P + 0.8 ns
0.25P +
0.8
0.25P +
0.8
0.25P +
0.8
DD16
td(CLK-DQML/UV)
Delay time, SDRAM.CLK transition to SDRAM.DQML/U valid Delay time, SDRAM.CLK transition to SDRAM.DQML/U invalid
1.3
1.3
1.3
1.3
1.3
ns
DD17
td(CLK-DQML/UIV)
1.3
1.3
1.3
1.3
1.3
1.3
ns
Timing values are given for the CONF_VOLTAGE_SDRAM_R bit of the VOLTAGE_CTRL_0 register programmed as follows: 0 for 1.8 V, 1 for 2.75/3.3 V. The maximum EMIFF/SDRAM clock rate is limited to the maximum traffic controller clock rate for the OMAP5912. Defined in the EMIFF DLL Write Control Register (DLL_PHASE bit). P = SDRAM.CLK (CLKX) period. Delay time assumes that WRITE_OFFSET bits value = 0 (in the DLL_URD_CONTROL and DLL_LRD_CONTROL registers).
December 2003 - Revised March 2004
SPRS231B
209
PRODUCT PREVIEW
Electrical Specifications
DD1 DD2 SDRAM.CLK SDRAM.CLKX
SDRAM.CKE DD3 SDRAM.CS DD4 SDRAM.RAS SDRAM.CAS DD6 SDRAM.BA[0:1] DD8 SDRAM.A[13:0] DD10 SDRAM.WE DD11 DD9 DD7 DD5 DD3
PRODUCT PREVIEW
Figure 5-32. EMIFF/DDR SDRAM - Command and Address Output Timing Definition
SDRAM.CLK SDRAM.CLKX SDRAM.DQSL SDRAM.DQSH (External) DLL Phase Control SDRAM.DQSL SDRAM.DQSH (Internal) DD12 SDRAM.D[15:0] DIN 0 DD13 DIN 1 DIN N
DQSL and DQSH internal delays are programmable in the EMIFF DLL_URD/LRD_CONTROL Register (72 to 90 degrees).
Figure 5-33. EMIFF/DDR SDRAM - Memory Read Timing
210
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
SDRAM.CLK SDRAM.CLKX
SDRAM.DQSL SDRAM.DQSH DD14 SDRAM.D[15:0] DOUT 0 DD16 SDRAM.DQML SDRAM.DQMU DOUT 1 DD17 DD15 DOUT N
This time includes the DLL phase effect on data, programmable in the EMIFF DLL Write Control Register (72 to 90 degrees), plus the device delay time (uncertainty).
Figure 5-34. EMIFF/DDR SDRAM - Memory Write Timing
December 2003 - Revised March 2004
SPRS231B
211
PRODUCT PREVIEW
Electrical Specifications
5.12 Multichannel Buffered Serial Port (McBSP) Timings 5.12.1 McBSP Transmit and Receive Timings
Table 5-21 and Table 5-22 assume testing over recommended operating conditions (see Figure 5-35 and Figure 5-36). In Table 5-21 and Table 5-22, "ext" indicates that the device pin is configured as an input (slave) driven by an external device and "int" indicates that the pin is configured as an output (master). Table 5-21. McBSP Timing Requirements
NO. M11 M12 tc(CKRX) tw(CKRX) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low McBSP1 M13 tr Rise time, CLKR/X, MCBSP2.FSR/X McBSP2 McBSP3 McBSP1 M14 tf Fall time, CLKR/X, MCBSP2.FSR/X McBSP2 McBSP3 McBSP1 (FSR) M15 tsu(FRH-CKRL) Setup time, external receiver frame sync (FSR/X) high before CLKR/X low McBSP2 (FSR) McBSP3 (FSX) McBSP1 (FSR) M16 th(CKRL-FRH) Hold time, external receiver frame sync (FSR/X) high after CLKR/X low McBSP2 (FSR) McBSP3 (FSX) McBSP1 M17 tsu(DRV-CKRL) Setup time, DR valid before CLKR/X low McBSP2 McBSP3
MIN CLKR/X ext CLKR/X ext CLKR/X ext CLKR/X ext, MCBSP2.FSR/X ext CLKR/X ext CLKR/X ext CLKR/X ext, MCBSP2.FSR/X ext CLKR/X ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext 17 20 17 5 16 10 2 7 2 2 9 9 14 2 15 2 13 7 2P 0.45P
MAX
UNIT ns ns
12 12 6 12 12 6 ns ns
PRODUCT PREVIEW
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration.
212
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Table 5-21. McBSP Timing Requirements (Continued)
NO. CLKX McBSP1 M18 th(CKRL-DRV) Hold time, DR valid after CLKR/X low McBSP2 McBSP3 McBSP1 M19 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low McBSP2 McBSP3 McBSP1 M20 th(CKXL-FXH) Hold time, external FSX high after CLKX low McBSP2 McBSP3
MIN int 2 2 2 2 2 2 20 17 19 18 19 18 2 7 2 2 2 2 CLKX ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKR int CLKR ext CLKX int CLKX ext
MAX
UNIT
ns
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration.
December 2003 - Revised March 2004
SPRS231B
213
PRODUCT PREVIEW
Electrical Specifications
Table 5-22. McBSP Switching Characteristics
NO. M0 M1 M2 M3 M4 td(CKSH-CKRXH) tc(CKRX) tw(CKRXH) tw(CKRXL) td(CKRH-FRV) PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high Pulse duration, CLKR/X low Delay time, CLKR high to internal FSR valid McBSP2 McBSP1 M5 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid McBSP2 McBSP3 McBSP1 M7 td(CKXH-DXV) Delay time, CLKX high to DX valid. This applies to all bits except the first bit transmitted when in Data Delay 0 (XDATDLY = 00b) mode. McBSP2 McBSP3 McBSP1 M9 td(FXH-DXV) Delay time, FSX high to DX Only applies to first bit transmitted when in Data Delay 0 (XDATDLY = 00b) mode. valid. McBSP2 McBSP3
MIN McBSP1 CLKR/X int CLKR/X int CLKR/X int CLKR/X int CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext FSX int FSX ext FSX int FSX ext 4 2P 0.90D 0.90C -1 -4 -2 5 0 5 -1 5 -1 5 1 6 -1 2
MAX 22
UNIT ns ns
1.10D 1.10C 9 10 9 26 3 16 6 25 5 27 7 18 7 11 19 17 20 18 7 18
ns ns ns
ns
PRODUCT PREVIEW
ns
ns
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. T = CLKRX period = (1 + CLKGDV) * P C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even Only DXENA = 0 is supported.
214
SPRS231B
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Electrical Specifications
MCBSP1.CLKS M0 M1, M11 M2, M12 M3, M12 MCBSPx.CLKR/X M4 MCBSP2.FSR (Internal) M13 MCBSPx.FSR/X (External) M15 M16 M18 M17 MCBSPx.DR (RDATDLY=00b) Bit (n-1) M17 M18 MCBSPx.DR (RDATDLY=01b) Bit (n-1) M17 M18 MCBSPx.DR (RDATDLY=10b) Bit (n-1) (n-2) (n-2) (n-3) (n-2) (n-3) (n-4) M14 M4 M14 M13
For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled via software configuration. The M13 and M14 descriptors are applicable only to McBSP2.
Figure 5-35. McBSP Receive Timings
December 2003 - Revised March 2004
SPRS231B
215
PRODUCT PREVIEW
Electrical Specifications
M1, M11 M2, M12 M3, M12 MCBSPx.CLKX M5 MCBSPx.FSX (Internal) M19 MCBSPx.FSX (External) M9 MCBSPx.DX (XDATDLY=00b) Bit 0 Bit (n-1) (n-2) M7 M7 MCBSPx.DX (XDATDLY=01b) Bit 0 Bit (n-1) (n-2) M7 (n-3) M20 M5
M13
M14
M7 (n-3) (n-4)
PRODUCT PREVIEW
MCBSPx.DX (XDATDLY=10b)
Bit 0
Bit (n-1)
(n-2)
Figure 5-36. McBSP Transmit Timings
216
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.12.2
McBSP as SPI Master or Slave Timings
Table 5-23 to Table 5-30 assume testing over recommended operating conditions (see Figure 5-37 to Figure 5-40). Table 5-23. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER NO. M30 M31 tsu(DRV-CKXL) th(CKXL-DRV) tsu(BFXL-CKXH) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX low Hold time, MCBSPx.DR valid after MCBSPx.CLKX low McBSP1 M32 M33
SLAVE MIN 2 - 6P 6 + 6P 20 5 15 ns ns MAX UNIT ns ns
MIN 15 2
MAX
Setup time, MCBSPx.FSX low before MCBSPx.CLKX high Cycle time, MCBSPx.CLKX
McBSP2 McBSP3 2P
16P
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.
Table 5-24. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER NO. M24 M25 M26 M29
SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns
PARAMETER th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX low Delay time, MCBSPx.FSX low to MCBSPx.CLKX high# Delay time, MCBSPx.CLKX high to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid
MIN 0.45T 0.45C -1
MAX 0.55T 0.55C 7
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even. FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX must be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). LSB CLKX M24 FSX M29 DX Bit 0 M30 M31 DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) Bit (n-1) (n-2) (n-3) (n-4) M25 M26 M32 MSB M33
Figure 5-37. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
December 2003 - Revised March 2004
SPRS231B
217
PRODUCT PREVIEW
Electrical Specifications
Table 5-25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER NO. M39 M40 tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXH) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high Hold time, MCBSPx.DR valid after MCBSPx.CLKX high McBSP1 M41 M42

SLAVE MIN 2 - 6P 6 + 6P 20 5 15 ns ns MAX UNIT ns ns
MIN 15 2
MAX
Setup time, MCBSPx.FSX low before MCBSPx.CLKX high Cycle time, MCBSPx.CLKX
McBSP2 McBSP3 2P
16P
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.
Table 5-26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER NO. M34 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) td(FXL-DXV) PARAMETER Hold time, MCBSPx.FSX low after MCBSPx.CLKX low Delay time, MCBSPx.FSX low to MCBSPx.CLKX high# Delay time, MCBSPx.CLKX low to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid MIN 0.45T 0.45C -1 MAX 0.55T 0.55C 7 D + 20 3P + 2 5P + 18 4P + 18 SLAVE MIN MAX UNIT ns ns ns ns
PRODUCT PREVIEW
M35 M36 M38
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even. D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even. FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX must be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). M41 M42
LSB MCBSPx.CLKX M24 MCBSPx.FSX
MSB
M35
M36
M38 MCBSPx.DX Bit 0 Bit (n-1) M39 M40 MCBSPx.DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4)
Figure 5-38. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
218
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
Table 5-27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER NO. M49 M50 tsu(DRV-CKXH) th(CKXH-DRV) tsu(FXL-CKXL) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high Hold time, MCBSPx.DR valid after MCBSPx.CLKX high McBSP1 M51 M52

SLAVE MIN 2 - 6P 6 + 6P 20 5 15 ns ns MAX UNIT ns ns
MIN 15 2
MAX
Setup time, MCBSPx.FSX low before MCBSPx.CLKX low Cycle time, MCBSPx.CLKX
McBSP2 McBSP3 2P
16P
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.
Table 5-28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER NO. M43 M44 M45 M48
SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns
PARAMETER th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX high Delay time, MCBSPx.FSX low to MCBSPx.CLKX low# Delay time, MCBSPx.CLKX low to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid
MIN 0.45T 0.45D -1
MAX 0.55T 0.55D 7
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. T = CLKX period = (1 + CLKGDV) * P D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even. FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX must be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX). LSB MCBSPx.CLKX M43 MCBSPx.FSX M48 MCBSPx.DX Bit 0 Bit (n-1) M49 M50 MCBSPx.DR Bit 0 Bit (n-1) (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) M44 M45 M51 MSB M52
Figure 5-39. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
December 2003 - Revised March 2004
SPRS231B
219
PRODUCT PREVIEW
Electrical Specifications
Table 5-29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER NO. M58 M59 tsu(DRV-CKXL) th(CKXL-DRV) tsu(FXL-CKXL) tc(CKX) Setup time, MCBSPx.DR valid before MCBSPx.CLKX low Hold time, MCBSPx.DR valid after MCBSPx.CLKX low McBSP1 M60 M61

SLAVE MIN 2 - 6P 6 + 6P 20 5 15 ns ns MAX UNIT ns ns
MIN 15 2
MAX
Setup time, MCBSPx.FSX low before MCBSPx.CLKX low Cycle time, MCBSPx.CLKX
McBSP2 McBSP3 2P
16P
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.
Table 5-30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
MASTER NO. PARAMETER th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) td(FXL-DXV) Hold time, MCBSPx.FSX low after MCBSPx.CLKX high Delay time, MCBSPx.FSX low to MCBSPx.CLKX low# Delay time, MCBSPx.CLKX high to MCBSPx.DX valid Delay time, MCBSPx.FSX low to MCBSPx.DX valid SLAVE MIN MAX UNIT ns ns 3P + 2 5P + 18 4P + 18 ns ns
PRODUCT PREVIEW
MIN 0.45D 0.45T -1
MAX 0.55D 0.55T 7 C + 20
M53 M54 M55 M57

For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1. P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2. T = CLKX period = (1 + CLKGDV) * P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even. D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even. FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # MCBSPx.FSX must be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (MCBSPx.CLKX).
M60 LSB MCBSPx.CLKX M53 MCBSPx.FSX M57 MCBSPx.DX Bit 0 M58 M59 MCBSPx.DR Bit 0 Bit (n-1) (n-2) Bit (n-1) (n-2) M54 M55 MSB
M61
(n-3)
(n-4)
(n-3)
(n-4)
Figure 5-40. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
220
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.13 Multichannel Serial Interface (MCSI)
Table 5-31 and Table 5-32 assume testing over recommended operating conditions (see Figure 5-41 and Figure 5-42). Table 5-31. MCSI Timing Requirements
NO. MC11 MC12 MC13 MC14 MC15 MC16 MC17 MC18 MC19

MIN fop(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) tsu(FSH-CLKL) th(CLKL-FSH) tsu(DIV-CLKL) th(CLKL-DIV) Operating frequency, MCSIx.CLK Pulse duration, MCSIx.CLK high Pulse duration, MCSIx.CLK low Rise time, MCSIx.CLK Fall time, MCSIx.CLK Slave Slave Slave Slave Slave 12 3,5 18 12 0 0 0.45P
MAX B
UNIT MHz ns ns ns ns ns ns ns ns
0.45P 0.55P 0.55P 12 12
Setup time, external MCSIx.SYNC high before MCSIx.CLK low Slave Hold time, external MCSIx.SYNC high after MCSIx.CLK low Setup time, MCSIx.DIN valid before MCSIx.CLK low Hold time, MCSIx.DIN valid after MCSIx.CLK low Slave Master Slave Master Slave
P = MCSIx.CLK period [tc(CLK)] in nanoseconds. B = Base frequency for OMAP5912 (12,13, or 19.2 MHz).
Table 5-32. MCSI Switching Characteristics
NO. MC1 MC2 MC3 MC4 MC7 MC8

PARAMETER fop(CLK) tw(CLKH) tw(CLKL) td(CLKH-FS) td(CLKH-DOV) ten(CLKH-DO) Operating frequency, MCSIx.CLK Pulse duration, MCSIx.CLK high Pulse duration, MCSIx.CLK low Delay time, MCSIx.CLK high to MCSIx.SYNC transition Delay time, MCSIx.CLK high to MCSIx.DOUT valid Enable time, MCSIx.DOUT driven from MCSIx.CLK high Master Master Master Master Master Slave Master Slave
MIN 0.45P 0.45P 0 0,5 6 0,5 6
MAX 0.5B 0.55P 0.55P 3 3 20
UNIT MHz ns ns ns ns ns
P = MCSIx.CLK period [tc(CLK)] in nanoseconds. B = Base frequency for OMAP5912 (12,13, or 19.2 MHz).
December 2003 - Revised March 2004
SPRS231B
221
PRODUCT PREVIEW
Electrical Specifications
1/MC1 MC2 MC3 MCSIx.CLK MC4 MCSIx.SYNC (normal short) MC4 MCSIx.SYNC (alt. short) MC4 MCSIx.SYNC (normal long) MC4 MCSIx.SYNC (alt. long) MC8 MCSIx.DOUT Bit (n) MC18 MCSIx.DIN Bit (n) MC18 MC19 (n-1) MC19 (0) MC7 (n-1) (0) MC4 MC4 MC4 MC4
PRODUCT PREVIEW
Figure 5-41. MCSI Master Mode Timings
1/MC11 MC12 MC13 MCSIx.CLK MC16 MCSIx.SYNC (normal short) MC16 MCSIx.SYNC (alt. short) MC16 MCSIx.SYNC (normal long) MCSIx.SYNC (alt. long) MC8 MCSIx.DOUT MC18 MCSIx.DIN Bit (n) MC18 Bit (n) MC19 (n-1) MC19 (0) MC7 (n-1) (0) MC16 MC17 MC17 MC17 MC15 MC14
M17
Figure 5-42. MCSI Slave Mode Timings
222
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.14 Serial Port Interface (SPI) Timings
Table 5-33 and Table 5-34 assume testing over recommended operating conditions (see Figure 5-43). Table 5-33. SPI Interface Timing Requirements
NO. SPI6 SPI7
MIN tsu(DV-CLKH) th(CLKH-DV) Setup time, SPIF.DIN valid before SPIF.SCK active edge Hold time, SPIF.DIN invalid after SPIF.SCK active edge 0 15
MAX
UNIT ns ns
Polarity of SPIF.SCK and the active clock edge (rising or falling) on which DOUT is driven and DIN data is latched is all software-configurable. These timings apply to all configurations regardless of SPIF.SCK polarity and which clock edges are used to drive output data and capture input data.
Table 5-34. SPI Interface Switching Characteristics
NO. SPI1 SPI2 SPI3 SPI4 SPI5
PARAMETER 1/top(SCLK) tw(SCLKH) tw(SCLKL) td(CS-SCLK) td(SCLK-DOUT) Operating frequency, SPIF.SCK Pulse duration, SPIF.SCK high Pulse duration, SPIF.SCK low Delay time, SPIF.CSx active to SPIF.SCK active in master mode Delay time, SPIF.SCK active edge to SPIF.DOUT transition
MIN 0.45P 0.45P 2 2
MAX B 0.55P 0.55P 5 5
UNIT MHz ns ns ns ns
B = system clock frequency of OMAP5912 (12, 13, or 19.2 MHz) P = period of SPIF.SCK in nanoseconds (ns).
SPIF.CSx SPI4 SPI2 SPIF.SCK SPI5 SPIF.DOUT Bit Out (n) SPI5 (n-1) SPI6 SPI6 SPIF.DIN Bit In (n) (n-1) (n-2) (n-3) 0 (n-2) (n-3) 0 SPI1 SPI3
SPI4
Figure 5-43. SPI Interface - Transmit and Receive in Master or Slave Timings
December 2003 - Revised March 2004
SPRS231B
223
PRODUCT PREVIEW
Electrical Specifications
5.15 VLYNQ Interface Timings 5.15.1 VLYNQ Slave Mode (External Clock Source)
Table 5-35 and Table 5-36 assume testing over recommended operating conditions. Table 5-35. VLYNQ as Slave Timing Requirements
NO. V1 V2 V3 V6 V7 V8 V9
MIN tc(CLK) tw(CLKH) tw(CLKL) tsu(RXV-CLKH) th(CLKH-DV) tr(RXCLKH) tf(RXCLKL) Clock period, VLYNQ.CLK Pulse duration, VLYNQ.CLK high Pulse duration, VLYNQ.CLK low Setup time, VLYNQ.RX[1:0] valid before VLYNQ.CLK high Hold time, VLYNQ.RX[1:0] valid after VLYNQ.CLK high Rise time, VLYNQ.RX[1:0] and VLYNQ.CLK Fall time, VLYNQ.RX[1:0] and VLYNQ.CLK 12.5 TBD TBD -0.65 2.2
MAX
UNIT ns ns ns ns ns
TBD TBD
ns ns
P = period of VLYNQ.CLK in nanoseconds (ns).
PRODUCT PREVIEW
Table 5-36. VLYNQ as Slave Switching Characteristics
NO. V4 V5 V10 V11
PARAMETER td(CLKH-TXV) td(CLKH-TXIV) tr(TXH) tf(TXLL) Delay time, VLYNQ.CLK high to VLYNQ.TX[1:0] valid Delay time, VLYNQ.CLK high to VLYNQ.TX[1:0] invalid Rise time, VLYNQ.TX[1:0] Fall time, VLYNQ.TX[1:0]
MIN 4
MAX 11.3 TBD TBD
UNIT ns ns ns ns
Maximum pin loading is assumed to be 15 pF (used for maximum VLYNQ_CLK to VLYNQ_TXD valid delay time).
224
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.15.2
VLYNQ Master Mode (Internal Clock Source)
Table 5-37 and Table 5-38 assume testing over recommended operating conditions (see Figure 5-44). Table 5-37. VLYNQ as Master Timing Requirements
NO. V6 V7 V8 V9 tsu(RXV-CLKH) th(CLKH-DV) tr(RXH) tf(RXL) Setup time, VLYNQ.RX[1:0] valid before VLYNQ.CLK high Hold time, VLYNQ.RX[1:0] valid after VLYNQ.CLK high Rise time, VLYNQ.RX[1:0] and VLYNQ.CLK Fall time, VLYNQ.RX[1:0] and VLYNQ.CLK MIN -0.65 1.75 TBD TBD MAX UNIT ns ns ns ns
Table 5-38. VLYNQ as Master Switching Characteristics
NO. V1 V2 V3 V4 V5 V12
PARAMETER tc(CLK) tw(CLKH) tw(CLKL) td(CLKH-TXV) td(CLKH-TXIV) tj(CLK) Clock period, VLYNQ.CLK Pulse duration, VLYNQ.CLK high Pulse duration, VLYNQ.CLK low Delay time, VLYNQ.CLK high to VLYNQ.TX[1:0] valid Delay time, VLYNQ.CLK high to VLYNQ.TX[1:0] invalid Cycle-to-cycle jitter, VLYNQ.CLK
MIN 10 TBD TBD 2.5
MAX TBD TBD 8 TBD
UNIT ns ns ns ns ps ns
P = period of VLYNQ.CLK in nanoseconds (ns). Maximum pin loading is assumed to be 15 pF (used for maximum VLYNQ_CLK to VLYNQ_TXD valid delay time).
V1 V2 VLYNQ.CLK V4 VLYNQ.TX[1:0] DOUT V6 V7 VLYNQ.RX[1:0] DIN V5 V3
Figure 5-44. VLYNQ Transmit and Receive Timings, in Slave or Master Mode
December 2003 - Revised March 2004
SPRS231B
225
PRODUCT PREVIEW
Electrical Specifications
5.16 Parallel Camera Interface Timings
Table 5-39 assumes testing over recommended operating conditions (see Figure 5-45). Table 5-39. Camera Interface Timing Requirements
NO. C1 C2 C3 C5 C6 C7 C8
MIN 1/[tc(LCKH-HSV)] 1/[tc(XCKH-HSV)] tw(LCK) tsu(LCKH-DV) th(DV-LCKH) tsu(LCKH-DV) th(DV-CLKH) Operating frequency, CAM.LCLK Operating frequency, CAM.EXCLK Pulse duration, CAM.LCLK high or low Setup time, CAM.D[7:0] data valid before CAM.LCLK high Hold time, CAM.D[7:0] data valid after CAM.LCLK high Setup time, CAM.VS/CAM.HS active before CAM.LCLK high Hold time, CAM.VS/CAM.HS active after CAM.LCLK high 6 0.45P 1 6 1 6
MAX 24 24 0.55P
UNIT MHz MHz ns ns ns ns ns
P = period of CAM.LCLK in nanoseconds (ns). Polarity of CAM.LCLK is selectable via the POLCLK bit in the CTRLCLOCK register. Although data is latched on rising CAM.LCLK in the timing diagrams, these timing parameters also apply to falling CAM.LCLK when POLCLK = 1.
PRODUCT PREVIEW
C3 CAM.LCLK C7 CAM.VS
C1 C3
C8
C7 CAM.HS C5 CAM.D[7:0] U1 Y1 V1 C6 C5
C8
C6 Yn
Figure 5-45. Camera Interface Timings
226
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.17 Compact Serial Camera Port (CCP) Timings
Table 5-40 assumes testing over recommended operating conditions (see Figure 5-46). Table 5-40. CCP Interface Timing Requirements
NO. C1 C2 C3 C4 C5 C6
MIN 1/[top(CLK)] tw(CLKLH) tw(CLKLL) tsu(DV-CLKH) th(CLKH-DV) VCM Operating frequency, CCP.CLK input frequency Pulse duration, CCP.CLK low Pulse duration, CCP.CLK high Setup time, CCP.DATA valid before CCP.CLK high Hold time, CCP.DATA valid after CCP.CLK high Input common mode voltage range 0.4P 0.4P 1 2 0.5
MAX 208 0.6P 0.6P
UNIT MHz ns ns ns ns
1.3
V
When nothing is being transferred, CLK has to remain high level, except in power shut-down. P = period of CAM.LCLK in nanoseconds (ns). 1/C1 C3 VIH VCM C4 C5 CCP.DATAM CCP.DATAP VIL VIH VCM VIL CCP.CLKM CCP.CLKP
Figure 5-46. CCP Interface Timing
December 2003 - Revised March 2004
SPRS231B
227
PRODUCT PREVIEW
C2
Electrical Specifications
5.18 LCD Controller and LCDCONV Interface Timings
Table 5-41 assumes testing over recommended operating conditions (see Figure 5-47 and Figure 5-48). Table 5-41. LCD Controller and LCDCONV Switching Characteristics
NO. L1 L2 L3 L4 td(CLKH-HSV) td(CLKL-HSV) td(CLKH-VSV) td(CLKL-VSV) PARAMETER Delay time, LCD.PCLK high to LCD.HS transition Delay time, LCD.PCLK low to LCD.HS transition Delay time, LCD.PCLK high to LCD.VS transition Delay time, LCD.PCLK low to LCD.VS transition Delay time, LCD.PCLK high to pixel data valid (LCD.P[15:0]) LCD 16-bit mode (LCDCONV bypassed) LCD 18-bit mode through LCDCONV (LCD.RED0 and LCD.BLUE0) LCD 16-bit mode (LCDCONV bypassed) LCD 18-bit mode through LCDCONV (LCD.RED0 and LCD.BLUE0) LCD 16-bit mode (LCDCONV bypassed) LCD 18-bit mode through LCDCONV (LCD.RED0 and LCD.BLUE0) LCD 16-bit mode (LCDCONV bypassed) LCD 18-bit mode through LCDCONV (LCD.RED0 and LCD.BLUE0) -10 ns -2 1 1 5 + P 5 + P ns ns -10 ns -2 -7 ns 7 MIN 1 1 1 1 MAX 7 7 7 7 -7 ns 7 UNIT ns ns ns ns
L5
td(CLKH-PV)
L6
td(CLKH-PIV)
Delay time, LCD.PCLK high to pixel data invalid (LCD.P[15:0])
PRODUCT PREVIEW
L7
td(CLKL-PV)
Delay time, LCD.PCLK low to pixel data valid (LCD.P[15:0])
L8
td(CLKL-PIV)
Delay time, LCD.PCLK low to pixel data invalid (LCD.P[15:0])
L9 L10
td(CLKH-ACV) td(CLKL-ACV)
Delay time, LCD.PCLK high to LCD.AC transition Delay time, LCD.PCLK low to LCD.AC transition
Although timing diagrams illustrate the logical function of the TFT mode, static timings apply to all supported modes of operation. Likewise, LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each can optionally be configured as active-high. P = period of internal undivided pixel clock
228
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December 2003 - Revised March 2004
Electrical Specifications
VSW HSW LCD.PCLK L4 LCD.VS L2 LCD.HS LCD.P[15:0] LCD.RED0 LCD.BLUE0 LCD.AC L5 D1 L9 D2 D3 Dn L9 L6 L4 VBP HBP HFP PPL
L2
Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VBP (Vertical Back Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch) and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers. The pins LCD.RED0 and LCD.BLUE0 are only available in 18-bit LCD mode (through LCDCONV interface).
Figure 5-47. TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK)
HSW LCD.PCLK
VSW
VBP
HBP
PPL
HFP
L3 LCD.VS L1 LCD.HS LCD.P[15:0] LCD.RED0 LCD.BLUE0 LCD.AC L1
L3
L7 D1 L10 D2 D3
L8 Dn L10
Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VBP (Vertical Back Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch) and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers. The pins LCD.RED0 and LCD.BLUE0 are only available in 18-bit LCD mode (through LCDCONV interface).
Figure 5-48. TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK)
December 2003 - Revised March 2004
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229
PRODUCT PREVIEW
Electrical Specifications
5.19 SoSSI Display Interface Timings
Table 5-42 and Table 5-43 assume testing over recommended operating conditions (see Figure 5-49 and Figure 5-50). Table 5-42. SoSSI Display Interface Timing Requirements
NO. SO3 SO4 tsu(DV-RDH) th(RDH-DV) Setup time, input SOSSI.Dx valid before SOSSI.RD high Hold time, input SOSSI.Dx valid after SOSSI.RD high MIN 25 0 MAX UNIT ns ns
Table 5-43. SoSSI Display Interface Switching Characteristics
NO. SO0 SO1 SO2
PARAMETER tc(CLKI) td(CMDV-WRV) td(WRH-DV) Cycle time, SoSSI internal clock Delay time, SOSSI.CMD to SOSSI.WR active Delay time, SOSSI.WR high to SOSSI.Dx transition
MIN 50
MAX P + 1 P+ 3.5
UNIT ns ns ns
P = period of internal clock interface in nanoseconds (ns).
PRODUCT PREVIEW
N Cycles P Cycles SOSSI.CS
N Cycles P Cycles
N Cycles
SOSSI.CMD SO1 SOSSI.WR
SOSSI.RD SO3 SO2 SOSSI.D[15:0] High-Z Command High-Z Dummy Read High-Z DIN SO4 High-Z

Numbers of cycles are configurable. Chip Select is controlled by software.
Figure 5-49. SoSSI Display Interface - Read Mode Operation
230
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
N Cycles P Cycles SOSSI.CS N Cycles P Cycles N Cycles
SOSSI.CMD SO1 SOSSI.WR
SOSSI.RD SO2 SOSSI.D[15:0] High-Z Command High-Z SO2 DOUT n High-Z DOUT n+1 High-Z

Figure 5-50. SoSSI Display Interface - Write Mode Operation
December 2003 - Revised March 2004
SPRS231B
231
PRODUCT PREVIEW
Numbers of cycles are configurable. Chip Select is controlled by software.
Electrical Specifications
5.20 Multimedia Card/Secure Digital (MMC/SD) Timings
Table 5-44 and Table 5-45 assume testing over recommended operating conditions (see Figure 5-51 through Figure 5-54). Table 5-44. MMC/SD Timing Requirements
NO. M1 M2 M3 M4 tsu(CMDV-CLKH) th(CLKH-CMDIV) tsu(DATV-CLKH) th(CLKH-DATIV) Setup time, MMC.CMD valid before MMC.CLK high Hold time, MMC.CMD invalid after MMC.CLK high Setup time, MMC.DATx valid before MMC.CLK high Hold time, MMC.DATx invalid after MMC.CLK high MIN 3.5 1 3.5 1 MAX UNIT ns ns ns ns
Table 5-45. MMC/SD Switching Characteristics
NO. M7 tc(CLK) tw(CLKL) tw(CLKH) td(CLKH-CMD) td(CLKH-DAT) PARAMETER MMC card Cycle time, MMC.CLK Pulse duration, MMC.CLK low Pulse duration, MMC.CLK high Delay time, MMC.CLK high to MMC.CMD transition Delay time, MMC.CLK high to MMC.DATx transition SD card MIN 50 40 0.45P 0.45P 8 8 0.55P 0.55P 32 32 ns ns ns ns ns MAX UNIT
PRODUCT PREVIEW
M8 M9 M10 M11
MMC.CLK period and pulse duration depend upon software configuration.
M7 MMC.CLK M10
M8
M9
M10 M10 M10 Valid Valid Valid END
MMC.CMD
START
XMIT
Figure 5-51. MMC/SD Host Command Timings
M7 MMC.CLK M1
M8
M9
M1 M2 M2 Valid Valid Valid END
MMC.CMD
START XMIT
Figure 5-52. MMC/SD Card Response Timings
232
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
M7 MMC.CLK M11 M11 MMC.DATx START D0 D1 D2 Dx END M11 M11 M8 M9
Figure 5-53. MMC/SD Host Write Timings
M7 MMC.CLK M3
M8
M9
M3 M4 M4 D1 D2 Dx END START
MMC.DATx
D0
December 2003 - Revised March 2004
SPRS231B
233
PRODUCT PREVIEW
Figure 5-54. MMC/SD Host Read and Card CRC Status Timings
Electrical Specifications
5.21 I2C Timings
Table 5-46 assumes testing over recommended operating conditions (see Figure 5-55). Table 5-46. I2C Signals (I2C.SDA and I2C.SCL) Switching Characteristics
NO. IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12 IC13 IC14 IC15

PARAMETER tc(SCL) tsu(SCLH-SDAL) th(SCLL-SDAL) tw(SCLL) tw(SCLH) tsu(SDA-SDLH) th(SDA-SDLL) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb Cycle time, I2C.SCL Setup time, I2C.SCL high before I2C.SDA low (for a repeated START condition) Hold time, I2C.SCL low after I2C.SDA low (for a repeated START condition) Pulse duration, I2C.SCL low Pulse duration, I2C.SCL high Setup time, I2C.SDA valid before I2C.SCL high Hold time, I2C.SDA valid after I2C.SCL low (for I2C bus devices) Pulse duration, I2C.SDA high between STOP and START conditions Rise time, I2C.SDA Rise time, I2C.SCL Fall time, I2C.SDA Fall time, I2C.SCL Setup time, I2C.SCL high before I2C.SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line
STANDARD MODE MIN 10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 4.0 400
FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 1.3 300 300 300 300 0.6 0 50 400 0.9 MAX
UNIT s s s s s ns s s ns ns ns ns s ns pF
MAX
PRODUCT PREVIEW
In the master-only I2C operating mode of OMAP5912, minimum cycle time for I2C.SCL is 12 s. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the I2C.SCL signal. Max of fall and rise times were measured while considering an internal pullup value of 520 . C = The total capacitance of one bus line in pF. b I2C.SDA IC8 IC4 IC10 I2C.SCL IC1 IC7 IC3 Stop Start Repeated Start IC12 IC3 IC2 IC5 IC6 IC14 IC13
Stop
NOTES: A. A device must internally provide a hold time of at least 300 ns for the I2C.SDA signal (referred to the VIHmin of the I2C.SCL signal) to bridge the undefined region of the falling edge of I2C.SCL. B. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the I2C.SCL signal. C. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SDLH) * 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C.SCL signal. If such a device does stretch the LOW period of the I2C.SCL signal, it must output the next data bit to the I2C.SDA line tr max + tsu(SDA-SDLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the I2C.SCL line is released. D. Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall times are allowed.
Figure 5-55. I2C Timings
234
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.22 Universal Serial Bus (USB) Timings
All OMAP5912 USB interfaces are compliant with Universal Serial Bus Specifications, Revision 1.1. Table 5-47 assumes testing over recommended operating conditions (see Figure 5-56). Table 5-47. USB Integrated Transceiver Interface Switching Characteristics
NO. U1 U2 U3 U4 U5 U6

PARAMETER tr tf tRFM VCRS tjr fop Rise time, USB.DP and USB.DM signals Fall time, USB.DP and USB.DM Rise/Fall time matching Output signal cross-over voltage Differential propagation Operating frequency jitter signals
LOW SPEED 1.5 Mbsp MIN 75 75 80 1.3 -25 MAX 300 300 125 2 25 1.5
FULL SPEED 12 Mbsp MIN 4 4 90 1.3 -2 MAX 20 20 111.11 2 2 12
UNIT ns ns % V ns MHz
REF clock tpx(0) USB.DM VCRS USB.DP VOH VOL tper - tjr 90% 10% U1
tpx(1)
U2
"REF clock" is not an actual device signal, but an ideal reference clock against which relative timings are specified. REF clock is assumed to be 12 MHz for full-speed mode or 1.5 MHz for low-speed mode.
Figure 5-56. USB Integrated Transceiver Interface Timings
December 2003 - Revised March 2004
SPRS231B
235
PRODUCT PREVIEW
Low speed: CL = 200 pF. High speed: CL = 50 pF. tRFM = (tr/tf) x 100 t =t jr px(1) - tpx(0) f = 1/t op per
Electrical Specifications
5.23 MICROWIRE Interface Timings
Table 5-48 and Table 5-49 assume testing over recommended operating conditions (see Figure 5-57). Table 5-48. MICROWIRE Timing Requirements
NO. W5 W6
MIN tsu(SDI-SCLK) th(SCLK-SDI) Setup time, UWIRE.SDI valid before UWIRE.SCLK active edge 16 1 Hold time, UWIRE.SDI invalid after UWIRE.SCLK active edge
MAX
UNIT ns ns
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software-configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data and capture input data.
Table 5-49. MICROWIRE Switching Characteristics
NO. W1 W2 W3 W4
PARAMETER fop(SCLK) tw(SCLK) td(SCLK-SDO) td(CS-SCLK) Operating frequency, UWIRE.SCLK Pulse duration, UWIRE.SCLK high/low Delay time, UWIRE.SCLK active edge to UWIRE.SDO transition Delay time, UWIRE.CSx active to UWIRE.SCLK active
MIN 0.45P -2 1.5P
MAX 0.25B 0.55P 4
UNIT MHz ns ns ns
PRODUCT PREVIEW
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software-configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data and capture input data. B = system clock of the OMAP5912 (12, 13, or 19.2 MHz). P = UWIRE.SCLK cycle time in nanoseconds (ns).
UWIRE.CSx W4 UWIRE.SCLK W2 W2 [1/W1] W4
W3 W3 UWIRE.SDO Valid Valid Valid W5 UWIRE.SDI Valid W6 Valid Valid
NOTE: The polarities of UWIRE.CSx and UWIRE.SCLK and the active UWIRE.SCLK edges on which SDO is driven and SDI is sampled are all software-configurable.
Figure 5-57. MICROWIRE Timings
236
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.24 HDQ/1-Wire Interface Timings
Table 5-50 and Table 5-51 assume testing over recommended operating conditions (see Figure 5-58 through Figure 5-63). Table 5-50. HDQ/1-Wire Timing Requirements
NO. H1 H2 H3 H4 W1 W2 W3
MIN tc tv tv tv tc tv tdis Cycle time, master read Read one data valid after HDQ low Read zero data hold after HDQ low OMAP5912 base frequency = 12 MHz Response time from HDQ slave device Cycle time, master read Read data valid after HDQ low (master sample window) Recovery time after slave device inactive OMAP5912 base frequency = 13 MHz 190 32 80 190 190 190 12 1
MAX 250 50 145 320 303 13.6
UNIT s s s s s s s s
HDQ timing is OMAP5912 default. 1-Wire timing is selectable through software.
Table 5-51. HDQ/1-Wire Switching Characteristics
NO. H5 H6 H7 H8 H9 W4 W5 W6 W7 tc td td tw tw tc td td tdis Cycle time, master write Write one data valid after HDQ low OMAP5912 base frequency = 12 MHz Write zero data hold after HDQ low Pulse width, HDQ low for break pulse (reset) Pulse width, HDQ high for break pulse recovery Cycle time, master write Write zero master inactive after HDQ low Write one master inactive after HDQ low Recovery time after master inactive OMAP5912 base frequency = 13 MHz PARAMETER MIN 190 32 100 92 190 40 190 15 1.1 1 90 1.4 50 145 145 MAX UNIT s s s s s s s s s s
Read 1 HDQ H2 H3 H1 Read 0
Figure 5-58. HDQ Interface Reading From HDQ Slave Device
Write 1 HDQ H6 H7 H5 Write 0
Figure 5-59. HDQ Interface Writing to HDQ Slave Device
December 2003 - Revised March 2004
SPRS231B
237
PRODUCT PREVIEW
Electrical Specifications
Break Command Byte (Written by OMAP5912) Register Address 0 (LSB) HDQ 1 6 7 (MSB) 0 (LSB) 1 6 7 (MSB) Data Byte (Received by OMAP5912 from Slave)
H4
Figure 5-60. Typical Communications Between OMAP5912 HDQ and HDQ Slave
HDQ H9 H8
PRODUCT PREVIEW
Figure 5-61. HDQ/1-Wire Break (Reset) Timings
OMAP5912 Master Active Low 1-Wire Slave Device Active Low Resistor Pull Up OMAP5912 Master Active Low Resistor Pull Up Read 0 HDQ W2 W3 W1 W1 W2 Read 1
Figure 5-62. 1-Wire Interface Reading From 1-Wire Slave Device
OMAP5912 Master Active Low Resistor Pull Up OMAP5912 Master Active Low Resistor Pull Up Write 0 HDQ W5 W7 W4 W4 W6 Write 1
Figure 5-63. 1-Wire Interface Writing to 1-Wire Slave Device
238
SPRS231B
December 2003 - Revised March 2004
Electrical Specifications
5.25 Embedded Trace Macrocell (ETM) Interface
Table 5-52 assumes testing over recommended operating conditions (see Figure 5-64 and Figure 5-65). Table 5-52. ETM Interface Switching Characteristics
NO. ETM1 ETM2 ETM3 ETM4 ETM5
PARAMETER tc(CLKI) tc(CLK) td(CLKIH-SYNCV) td(CLKH-PSTATV) td(CLKH-DV) Cycle time, ETM internal clock Cycle time, ETM.CLK (external) clock Delay time, ETM clock high to ETM.SYNCx transition Delay time, ETM clock high to ETM.PSTATx transition Delay time, ETM clock high to ETM.Dx transition
MIN 5 10
MAX
UNIT ns ns
0.5P + 0.39 0.5P + 0.45 0.5P + 0.87
ns ns ns
P = internal clock period
ETM1 Internal ETM Clock ETM2 ETM.CLK ETM3 ETM.SYNC[0] ETM4 ETM.PSTAT[2:0] ETM5 ETM.D[7:0] ETM5 ETM4 ETM3
The signal shown represents the internal ETM clock signal given as a reference to express delay time.
Figure 5-64. Normal Mode - Half Rate Clock - Rising and Falling Clock Edge
December 2003 - Revised March 2004
SPRS231B
239
PRODUCT PREVIEW
Electrical Specifications
ETM1 Internal ETM Clock ETM2 ETM.CLK ETM3 ETM.SYNC[0] ETM4 Trace Data A ETM.PSTAT[2:0] ETM5 ETM.D[3:0] ETM3 ETM.SYNC[1] ETM4 ETM4 ETM3 ETM5 ETM4 ETM3
PRODUCT PREVIEW
Trace Data B
ETM.PSTAT[5:3] ETM5 ETM.D[7:4] ETM5
The signal shown represents the internal ETM clock signal given as a reference to express delay time.
Figure 5-65. Demultiplexed Mode of Full Rate Clock - Rising Clock Edge
240
SPRS231B
December 2003 - Revised March 2004
Glossary
6
3DES AAC AC97 ALE ALU AMR APE APLL
Glossary
DEFINITION triple data encryption security Advanced Audio Coding (standard) (ISO/IEC 13818-7) Interface Standard for Codecs address latch enable arithmetic/logic unit adaptive multi-rate application chip analog phase-locked loop asynchronous static random-access memory address unit binary coded decimal built-in self-test cipher block chaining compact camera port chip enable cipher feedback common latch enable complementary metal oxide semiconductor cellular mobile telephone coprocessor 15 central processing unit cyclic redundancy check chip select Chip Support Library clear-to-send dual-access random-access memory digitally controlled delay element discrete cosine transform dual data rate data encryption security direct memory access digital phase-locked loop digital signal processor DSP Library data-set-ready data-terminal-ready data unit ball grid array
ACRONYM
ASRAM AU BCD BGA BIST CBC CCP CE CFB CLE CMOS CMT CP15 CPU CRC CS CSL CTS DARAM DCDL DCT DDR DES DMA DPLL DSP DSPLIB DSR DTR DU
December 2003 - Revised March 2004
SPRS231B
241
PRODUCT PREVIEW
Glossary
ACRONYM ECB EEPROM EMIFF EMIFS EOF EP ESD ETM FAC FFT FIFO FIQ FIR
DEFINITION electronic codebook electrically erasable programmable read-only memory external memory interface fast external memory interface slow end of file endpoint electrostatic discharge Embedded Trace Macrocell frame adjustment counter Fast Fourier Transform first-in first out fast interrupt request fast infrared Generic Distribute DMA general-purpose general-purpose input/output General Packet Radio Service Global System for Mobile Communications an ITU-TSS standard Human Body Model host controller host controller interface host-only mode high-speed instruction cache Inter-integrated circuit Inter-IC Sound (specification) Inverse Discrete Cosine Transform integrated development environment interface Interrupt Flag Register Image/Video Processing Library Interrupt Mask Register input/output ISDN Oriented Modular Interface Revision 2 infrared data adapter interrupt request instruction unit initialization vector
PRODUCT PREVIEW
GDD GP GPIO GPRS GSM H.26x HBM HC HCI HOM HS I-cache I2C I2S iDCT IDE I/F IFR IMGLIB IMR IO IOM-2 IrDA IRQ IU IV
242
SPRS231B
December 2003 - Revised March 2004
Glossary
ACRONYM JPEG JTAG LB LCD LH LPG LSB LVCMOS MAC McBSP MCSI MD5 MeSSI MIR MMC MMC/SD MMU MPEG MPU MPUI MPUIO MSB MVIP OCP ODM OEM OFB OHCI OS OTG PCM PI PU PWL PWM PWT
DEFINITION Joint Photographic Experts Group Joint Test Action Group, IEEE 1149.1 standard local bus liquid-crystal display local host LED pulse generator light pulse generation least significant bit low-voltage CMOS multiply-accumulate multichannel buffered serial port multichannel serial interface Message-Digest Algorithm developed by R. Rivest medium infrared multimedia card multimedia card/secure digital multimedia card/secure data memory management unit Moving Picture Experts Group microprocessor unit microprocessor unit interface microprocessor unit I/O most significant bit multi-vendor integration protocol open core protocol original design manufacturer original equipment manufacturer output feedback open host controller interface operating system on-the-go pulse code modulation pixel interpolation program unit pulse-width light pulse width length pulse width modulation pulse-width tone pulse width time
December 2003 - Revised March 2004
SPRS231B
243
PRODUCT PREVIEW
medium speed screen interface
Glossary
ACRONYM R/B RAM RE RGB RISC RNG ROM RTC RTS RX SAM SARAM SD
DEFINITION read/busy random-access memory read enable red green blue reduced instruction set computer random number generator read-only memory real-time clock request-to-send receive shared-access mode single-access random-access memory secure digital single data rate synchronous dynamic random-access memory short distance wireless slow infrared specially optimized screen interface serial port interface serial peripheral interface static random-access memory Sample Rate Generator synchronous serial interconnect synchronous serial receiver synchronous serial transmitter super twisted nematic T1 is a digital transmission link with a capacity of 1.544 Mbps. It uses two pairs of normal twisted-wires and can handle 24-voice conversations, each digitized using mu-law coding at 64 kbps. T1 is used in USA, Canada, Hong Kong, and Japan. E1 is a digital transmission link with a capacity of 2.048 Mbps. It is the European equivalent of T1. It can handle 30-voice conversations, each digitized using A-law coding at 64 kbps. test access port traffic controller triple data encryption security thin-film transistor Texas Instruments TI peripheral bus Translation Look-Aside Buffer Translation Table Base transmit
PRODUCT PREVIEW
SDR SDRAM SDW SIR SoSSI SPI SRAM SRG SSI SSR SST STN T1/E1
TAP TC TDES TFT TI TIPB TLB TTB TX
244
SPRS231B
December 2003 - Revised March 2004
Glossary
ACRONYM UART ULPD URL USB VIA VIVT WB WDT WE WMA WMV WP
DEFINITION universal asynchronous receiver/transmitter ultra low-power device uniform resource locator universal serial bus versatile interconnection architecture virtual index virtual tag write buffer watchdog timer write enable Windows Media Audio Windows Media Video write protect
December 2003 - Revised March 2004
SPRS231B
245
PRODUCT PREVIEW
Mechanical Data
7
7.1
Mechanical Data
Ball Grid Array Mechanical Data
PLASTIC BALL GRID ARRAY
ZDY (S-PBGA-N289)
19,20 SQ 18,80 17,70 SQ 17,30 11,80 SQ 11,40 U T R P N
16,00 TYP 1,00
PRODUCT PREVIEW
M L K J H G F E D A1 Corner B A 1 2 1,22 1,12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 C 1,00
Bottom View 0,61 0,51 2,32 MAX Seating Plane 0,60 0,40 0,10 0,15
0,50 0,30
4205390/A 09/03
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. This package is lead free.
Figure 7-1. OMAP5912 289-Ball Plastic Ball Grid Array Package (ZDY)
246
SPRS231B
December 2003 - Revised March 2004
Mechanical Data
ZZG (S-PBGA-N289)
PLASTIC BALL GRID ARRAY
12,10 SQ 11,90
10,00 TYP 0,50
Y V T P M K H F D B
AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 Bottom View 0,50
A1 Corner 0,95 0,85
1,20 MAX Seating Plane 0,35 0,25 0,05 0,30 0,20 0,08
4204397-3/A 04/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration D. This package is lead-free.
Figure 7-2. OMAP5912 289-Ball MicroStar BGAE Plastic Ball Grid Array Package (ZZG)
MicroStar BGA is a trademark of Texas Instruments. 247
December 2003 - Revised March 2004
SPRS231B
PRODUCT PREVIEW


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